Ranges can be defined as inclusive, as shown
in
the preceding examples, or exclusive, using
DBCRO[IA12X] (corresponding to range 1 :2) and DBCRO[IA34X] (corresponding to range 3:4), as
follows:
DBCRO[IA
12] =
1:
Range 1 :2 =
IAC1
::;
range < IAC2.
DBCRO[IA12X]
=
1:
Range 1:2 = Range low <
IAC1
or IAC2::; Range high
DBCRO[IA34] =
1:
Range 3:4 = IAC3
::;
range < IAC4.
DBCRO[IA34X]
=
1:
Range 3:4 = Range low < IAC3 or IAC4
::;
Range high
Figure
12-10 shows the range selected
in
an inclusive lAC range address compare. Note that the
address
in
IAC1
is considered part of the range, but the address
in
IAC2 is not, as shown in the
preceding
examples. The thick lines indicate that the indicated address is included
in
the compare
results.
o
FFFF
FFFF
I
IAC1
IAC2
Figure 12-10. Inclusive lAC Range Address Compares
Figure 12-11 shows the range selected
in
an inclusive lAC range address compare. Note that the
address
in
IAC1
is not considered part of the range, but the address
in
IAC2 is, along with the highest
memory address, as shown
in
the preceding examples.
o
FFFF FFFF
I
I
IAC1
IAC2
Figure 12-11. Exclusive lAC Range Address Compares
To
toggle the range from inclusive to exclusive or from exclusive to inclusive on a lAC range debug
event,
OBCRO[IA 12T] (corresponding to range 1 :2) and DBCRO[IA34T] (corresponding to range 3:4)
are used.
If these fields are set, the DBCRO[IA 12X]
or
DBCRO[IA34X] fields toggle
on
an lAC debug
event, changing the defined range.
When a
toggle is enabled (DBCRO[IA12T] for range 1:2
or
DBCRO[IA34T] = 1 for range 3:4), and
DBCRO[IDM] =1, DBCRO[EDM] =
0,
and MSR[DE] = 0, lAC range comparisons for the corresponding
toggle field are disabled.
12.9.13 DAe Debug Event
This debug event occurs before execution of an instruction that accesses a data address that
matches the contents of the specified DAC register. DBCR1
[D1
R,
D2R, D1W,
02W]
enable DAC
debug events for address comparisons on
DAC1
and DAC2 for read instructions, DAC2 for read
instructions,
DAC1
for write instructions, DAC2 for write instructions respectively. Loads are reads and
stores are writes. DAC can be defined(DBCR1
[01
R,
D2R])as an exact address comparison to one of
the DACn registers
or
a range of addresses to compare defined by
DAC1
and OAC2 registers.
12·18
PPC405GP
User's
Manual
Preliminary
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