• PowerPC Operating Environment Architecture, including the memory management model,
supervisor-level
registers, and the exception model. These features are not accessible from the
user
level. This is referred to as Book
III
of the PowerPC Architecture.
Book
I and Book
II
define the instruction set and facilities available to the application programmer.
Book
III
defines features, such as system-level instructions, that are not directly accessible by user
applications. The PowerPC Architecture is described
in
The PowerPC Architecture: A Specification
for a New Family
of
RISe
Processors.
The PowerPC Architecture provides compatibility of PowerPC Book I application code across all
PowerPC implementations to help maximize the portability of applications developed for PowerPC
processors. This is
accomplished through compliance with the first level of the architectural definition,
the PowerPC
UISA, which is common to all PowerPC implementations:
1.3 The PPC405GP
as
a PowerPC Implementation
The PPC405GP implements the PowerPC UISA, user-level registers, programming model, data
types, addressing modes, and 32-bit fixed-point operations. The
PPC405GP fully complies with the
PowerPC
UISA. The UISA 64-bit and floating point operations are not implemented. The floating point
operations, which cause exceptions, can then be
emulated by software.
Most of the features of the
PPC405GP processor core are compatible with the PowerPC Virtual
Environment and Operating Environment Architectures, as implemented
in
PowerPC processors such
as the 6xxl7xx family. The
PPC405GP processor core also provides a number of optimizations and
extensions
to
these layers of the PowerPC Architecture. The full architecture of the PPC405GP is
defined by the PowerPC Embedded Environment and the PowerPC User
Instruction Set Architecture.
The primary extensions of the PowerPC Architecture defined
in
the Embedded Environment are:
• A simplified memory management mechanism with enhancements for embedded applications
•
An
enhanced, dual-level interrupt structure
•
An
architected OCR address space for integrated peripheral control
•
The addition of several instructions to support these modified and extended resources
Finally, some of the specific implementation features of the PPC405GP are beyond the scope of the
PowerPC Architecture. These features are
included to enhance performance, integrate functionality,
and reduce system
complexity
in
embedded control applications.
1.4
RISC
Processor Core Organization
The processor core consists of a 5-stage pipeline, separate instruction and data cache units, virtual
memory management unit (MMU), three timers, debug, and interfaces to other functions.
1.4.1
Instruction and Data Cache Controllers
The PPC405GP processor core uses a 16KB instruction cache unit (ICU) and an 8KB data cache unit
(OCU) to
enable concurrent accesses and minimize pipeline stalls. Both cache units are two-way set-
associative and use a 32-byte
line size. The instruction set provides a rich assortment of cache
control instructions, including instructions to read tag information and data arrays. See Chapter 4,
"Cache Operations," for detailed information about the ICU and
OCU.
Preliminary Overview 1-5
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