IBM PowerPC 405GP User Manual

Chapter 13. Clock and Power Management
The PPC405GP provides a clock and power management (CPM) controller that reduces power
dissipation by stopping
clocks in unused or dormant functional units. Use of the CPM controller
requires careful programming and special consideration to avoid compromising system and functional
unit integrity.
The CPM
controller supports three different types of sleep interfaces to the functional units:
• In a CPM class 1 interface, the CPM_Sleep_N signal is asserted by the CPM controller when a
register bit is set by software. The
functional unit is unconditionally put to sleep. There is no other
communication with the
functional unit.
• In a CPM class 2 interface, the functional unit uses a combination of its internal state and external
inputs to determine whether or not it can be put to sleep. If sleeping is permitted, the functional unit
asserts the
Sleep_Req signal to the CPM controller that responds by asserting CPM_Sleep_N if
the
enable for that unit is set. The CPM_Sleep_N signal to a class 2 unit is deasserted when the
CPM
controller enable bit for that unit is reset, or when the unit deasserts its Sleep_Req signal.
•
The CPM class 3 interface has a CPM_Sleeplnit signal that is asserted by the CPM controller to
request that a
functional unit go to sleep. If the unit can sleep, it asserts the Sleep_Req signal to
the CPM
controller. The CPM_Sleep_N signal is then asserted by the CPM controller to shut off the
class 3 clocks in the functional unit. The functional unit or the CPM controller can end the sleep
state. If the CPM controller enable bit for the unit is reset, the CPM controller immediately
deasserts CPM_Sleeplnit and CPM_Sleep_N.
13.1 CPM Registers
Table 13-1 lists the registers used to program the CPM controller.
Table 13-1. CPM Registers
Reset Value (0:16)
Register Name
OCR Address Access (bits 17:31 reserved)
CPCO_ER
OxOB9 Read/Write OxOOOOxxxx
CPCO_FR
OxOBA Read/Write
OxOOOOxxxx
CPCO_SR
OxOB8 Read Only OxFFFFxxxx
Each f.unctional unit has one bit in each of CPCO_ER, CPCO_FR, and CPCO_SA. The bit assignment
is the same
in the three registers. Figure 13-1 shows the bit assignment and CPM class for each
PPC405GP
functional units.
Preliminary Clock and Power Management
13-1

IBM PowerPC 405GP Specifications

General

Brand	IBM
Model	PowerPC 405GP
Category	Computer Hardware
Language	English