17:18
BW
Bus
Width
00
8-bit
bus
01
16-bit
bus
10
32-bit
bus
11
Reserved
..
19:31
Reserved
•
BAS
(Base
Address
Select,
bits
0:11) - Sets the base address for a peripheral device. The bank
starting address must be a multiple of the bank size programmed in the BS field. The BAS
fie.ld
is
compared to bits
0:
11
of the address. If the address is within the range
of
a BAS field, the
associated bank is enabled for the transaction.
Multiple bank registers may be inadvertently programmed with the same base address or as
overlapping banks. An attempt to use such overlapping banks is recorded in
EBCO_BESRO
or
EBCO_BESR1 as a configuration error and no external access occurs. This error may result in a
machine check exception if the requesting master is the CPU.
If the error occurred during a DMA
access, the DMA may signal an interrupt to the
PPC405GP through the UIC.
•
BS
(Bank
Size,
bits
12:14) - Sets the number of bytes which the bank may access, beginning with
the base address set in the BAS field.
• BU (Bank Usage, bits 15:16) - Protects banks of physical devices from read or write accesses.
When a write access is attempted to an address within the range
of
the BAS field, and the bank is
designated as read-only, a protection error occurs. Also, when a read access is attempted to an
address within the range of the BAS field, and the bank is designated as write-only, a protection
error occurs. The address of the attempted access is logged
in
EBCO_BEAR and type
of
error is
logged in either
EBCO_BESRO or EBCO_BESR1.
•
BW
(Bus Width, bits 17:18) - Controls the width of region accesses. If the BW field is
ObOO,
the
region is configured for an 8-bit data bus;
Ob01
indicates a 16-bit data bus and
Ob1
0 indicates a 32-
bit data bus.
If devices are attached to the data bus as shown in Figure 16.1.1 on page 16-3, the
EBC automatically packs read data and unpacks write data when a data transfer size mismatch
exists.
16.6.3 Peripheral Bank Access Parameters (EBCO_BnAP)
BME
TWT
CSN
WBN
TH
SOR
PEN
+ +
+ + + + +
1
0
1
1
5 6
81
9
11112
13114
15116
17118
19
1
20
22123124125126127
31
1
t t
t t
t t
FWT
BWT
OEN
WBF
RE
BEM
Figure
16-17.
Peripheral
Bank
Access
Parameters
(EBCO_BnAP)
0
BME
Burst
Mode
Enable
o Bursting
is
disabled
1 Bursting
is
enabled
1
:8
TWT
Transfer
Wait
Wait
states
on
all
transfers
when
BME=O.
0-255
PerClk
cycles
16-26
PPC405GP
User's
Manual
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