Chapter 16. External Bus Controller
The PPC405GP External Sus controller (ESC) provides direct attachment for most SRAM/Flash type
memory and
peripheral devices. The interface minimizes the amount of external glue logic needed to
communicate with memory and
peripheral devices. This reduces the embedded system device count,
circuit board area, and cost.
To
eliminate off-chip address decoding, the ESC provides eight programmable chip selects that
enable system designers to locate memory and peripherals within the PPC405GP memory map. Chip
select, data bus, and associated control signal timings are programmable for both single and burst
transfers. For
peripherals with variable timing requirements the ESC supports device-paced transfers
with
optional bus-timeout. System design is further simplified through dynamic bus sizing which
supports
seamlessly attaching 8-, 16-, and 32-bit wide memories and peripherals. Whenever a size
mismatch exists between a read
or
write operation and the externally attached device, the ESC
automatically
packs or unpacks data as appropriate.
In
addition to the peripheral and memory interface, the ESC includes an external bus master (ESM)
interface. Using the ESM, external masters arbitrate and gain access to the peripheral interface. Once
an external master owns the peripheral interface it can read and write all PLS- and OPS-addressable
memory, with the exception of devices controlled by the ESC. Typical destinations for ESM
transactions are
PCI
address space and SDRAM memory. For ESC-attached peripherals and
memory, the
external master is required to directly control the target.
16.1
Interface Signals
Figure 16-1 on page 16-2 illustrates the signal
110
between the ESC and the external peripheral bus.
External Bus Controller
16-1
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