IBM PowerPC 405GP User Manual

2.1.6 PLB Arbiter Registers
PLB arbiter registers are OCRs accessed using the mfdcr and mtdcr instructions.
Table 2-3 summarizes the PLB arbiter
OCRs.
Table
2-3. PLB Arbiter Registers
Mnemonic
Register Name Address
PLBO_ACR
PLB Arbiter Control Register
Ox087
PLBO_BEAR
PLB Error Address Register
Ox086
PLBO_BESR
PLB Error Status Register
Ox084
2.1.6.1 PLB Arbiter Control Register (PLBO_ACR)
Access Page
RIW
2-5
RIO 2-5
RlClear 2-6
The PLBO_ACR controls PLB arbitration priority, which is determined by PLB priority mode and PLB
priority order.
PPM HBU
*
*
Figure 2-2. PLB Arbiter Control Register (PLBO_ACR)
0 PPM PLB Priority Mode
o Fixed
1 Fair
1:3
PPO PLB Priority Order
000
Masters 0, 1, 2, 3, 4, 5
001 Masters 1, 2, 3, 4, 5, 0
010
Masters 2, 3, 4, 5, 0, 1
011 Masters 3, 4, 5,0, 1, 2
100 Masters 4, 5, 0, 1, 2, 3
101 Masters 5, 0, 1, 2, 3, 4
110 Reserved
111 Reserved
4
HBU High Bus Utilization
o Disabled
1 Enabled
5:31
Reserved
2.1.6.2 PLB Error Address Register (PLBO_BEAR)
The read-only PLBO_BEAR contains the address of the access on which a bus timeout error
occurred.
The PLBO_BEAR can be locked by the master.
Once locked, the PLBO_BEAR cannot be updated, if a
subsequent error occurs, until all PLBO_BESR[FLCKn] fields are cleared
(n is the master 10).
Preliminary
On-Chip Buses 2-5

IBM PowerPC 405GP Specifications

General

Brand	IBM
Model	PowerPC 405GP
Category	Computer Hardware
Language	English