Chapter 18. Direct Memory Access Controller
The Direct Memory Access (DMA) controller is a Processor Local Sus (PLS) and On-chip Peripheral
Sus (OPS)
master which supports the autonomous transfer of data between memory and peripherals
and from memory-to-memory. The controller provides four DMA channels, each of which has an
independent set of configuration registers. Each
channel has its own control, source address,
destination address, count, and scatter/gather address registers.
Once these registers are
programmed by the
PPC405 processor, the DMA controller performs the requested data transfer
without the need for processor intervention.
The four DMA
channels also support scatter/gather transfers. During a scatter/gather transfer the
configuration registers for a
particular DMA channel are automatically loaded from a data structure in
memory instead of being
individually programmed. Since the scatter/gather address register is
updated
in
this process, the channel can optionally reconfigure itself for another transfer when the
current one
completes.
As master on both the PLS and OPS the DMA controller can read and write any address accessible
by the PPC405 processor. This includes memory and memory-mapped peripherals on the ESC
interface, SDRAM memory and PCI addresses that have been mapped into PLS address space. The
DMA
controller can also service DMA peripherals attached to the ESC via the DMAReqn, DMAAckn
and EOTn[TCn]
I/Os, along with the OPS-attached
UARTO.
18.1
External Interface Signals
Figure 18-1 illustrates the externall/Os associated with the DMA controller and the ESC I/Os used
during
external peripheral transfers. External peripheral and ESC device-paced memory transfers
request service from the DMA
controller by driving a DMA request line (DMAReqO-3) active. For
peripheral mode transfers the DMA controller acknowledges the request and transfers data by
asserting a DMA
acknowledge signal (DMAAckO-3). In contrast, an ESC device-paced memory-to-
memory transfer occurs when the chip
select (PerCSn) associated with the memory location is driven
active. The timing of
PerCSn and the other ESC I/Os is determined by the Sank Access Parameter
Register
(ESCO_SnAP) for the particular memory location. See Chapter 16, "External Sus Controller"
for details on ESC configuration and timings.
Table 18-1.
DMA
Controller
External
II0s
Signal
Usage
DMAAckn
DMA Request, used to request either a peripheral mode transfer or an
ESC device-
paced memory-to-memory transfer.
DMAAckn DMA Acknowledge, instructs an ESC-attached DMA peripheral to transfer data.
End of Transfer or Terminal Count. Used to stop the channel when programmed as
EOTn[TCn]
EOT.
When configured as TC, goes active when the channel transfer count register
(DMAO_CTn) reaches zero.
Note
1: The active level (polarity) of DMAReqn, DMAAckn, and EOTn[TCn] are individually
programmable. See "DMA Polarity Configuration Register (DMAO_POL)" on page 18-5.
Preliminary Direct Memory Access Controller
18-1
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