EasyManuals Logo

IBM PowerPC 405GP User Manual

IBM PowerPC 405GP
668 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Page #531 background imageLoading...
Page #531 background image
Figure 19-8 illustrates the control packet format.
Preamble SPD
DA
Preamble - Alternating zeroes and ones (7 bytes)
SPD
(Start Of Packet Delimiter). 1 byte
DA
(Destination Address) = Ox0180C2000001
SA (Source Address) = Universally Administered Address (UAA)
LengthfType
= Ox8808
Opcode Field =
Ox0001
Timer Value Field = PauseValue
Reserved = zeroes (42 bytes)
FCS = calculated FCS
Reserved FCS
Figure 19-8. Control Packet Format
The timer value field contains the value of the delay interval in resolution of pause_quanta, defined in
IEEE 802.3x as follows: "MAC Control Parameter[s] (pause_time) is a 2-octet, unsigned integer
containing the length of time for which the receiving station is requested to inhibit data packet
transmission. The field is transmitted most-significant octet first, and least-significant octet second.
The pause_time is measured
in
units of pause_quanta, equal to 512 bit times. The range of possible
pause_time is
ยฐ to 65535 pause_quanta."
19.5.2 Control Packet Transmission
There are two options to initiate the transmission of a pause packet from EMAC. The transmitted
pause packet will force the node, with the destination address specified, to temporarily suspend the
transmission of packets to EMAC.
โ€ข Option 1
Software initiated. The packet transferred to EMAC by MAL for transmission is a pause packet
created by software. EMAC transmits this as a normal packet.
โ€ข Option 2
Automatic flow control initiated. The EMAC integrated flow control mechanism detects the need for
and then transmits a control (pause) packet automatically. When building the control packet, EMAC
obtains the
SA
(source address) field from the Individual Address Registers (EMACO_IAHR and
EMACO_IALR), and the timer value from the Pause Timer Register (EMACO_PTR[TVF]). The
contents of the other fields
in
the packet are represented
in
Figure 19-8.
19.5.3 Integrated Flow Control
To
enable integrated flow control
in
full-duplex mode, set EMACO_MR1 [EIFC] = 1. When the receive
FIFO reaches a predefined threshold level (called a high water mark and specified by
EMACO_RWMR[RHWM]), an internal request for control (pause) packet transmission is activated.
EMAC sends a control (pause) packet when a new packet enters the Receive
FIFO and the number
of vacant entries in the Receive
FIFO is less than the high water mark. When the Receive FIFO
reaches another predefined threshold level (the low water mark, specified by
19-16 PPC405GP User's Manual
Preliminary

Table of Contents

Questions and Answers:

Question and Answer IconNeed help?

Do you have a question about the IBM PowerPC 405GP and is the answer not in the manual?

IBM PowerPC 405GP Specifications

General IconGeneral
BrandIBM
ModelPowerPC 405GP
CategoryComputer Hardware
LanguageEnglish

Related product manuals