3.3.10.2 Indirectly Accessed MMIO Registers
The PCI configuration registers, listed in Table 3-15, are indirectly accessed.
The
following procedure accesses the PCI configuration registers, using the address and data
registers
listed
in
Table 3-14:
1.
OR the Enable, Bus, Device, and Function fields of the PCI Configuration Address Register
(PCICO_CFGADDR) with the high-order 6 bits of the offset from Table 3-15 and write the result to
the
PCICO_CFGADDR.
2.
OR the low-order 2 bits of the offset from Table 3-15 with the address of the
PCI
Configuration Data
Register
(PCICO_CFGDATA) to form an address.
3.
Read data from
or
write data to the address.
Table 3-14.
PCI
Configuration Address and Data Registers
Register
Address
Access
Description
PCICO_CFGADDR
OxEECOOOOO
R/W
PCI Configuration Address Register
PCICO_CFGDATA
OxEECOOOO4
RIW
PCI
Configuration Data Register
Table 3-15.
PCI
Configuration Registers
Access
Register
Offset
PLB
PCI
Description
PCICO_ VENDID Ox01-0xOO RIW R PCI Vendor ID
PCICO_DEVID Ox03-0x02 RIW
R
PCI Device ID
PCICO_CMD Ox05-0x04 RIW RIW
PCI
Command Register
PCICO_STATUS Ox07-0x06
RIW RIW
PCI Status Register
PCICO_REVID
Ox08
RIW RIW
PCI
Revision ID
PCICO_CLS OxOB-Ox09 RIW
R
PCI Class Register
PCICO_CACHELS
OxOC
R R
PCI Cache Line Size
PCICO_LATTIM
OxOD
RIW RIW
PCI
Latency Timer
PCICO_HDTYPE
OxOE
R R PCI Header Type
PCICO_BIST
OxOF
R R
PCI Built
In
Self Test Control
PCICO_
BARO
Ox13-0x10 R R PCI Reserved BAR 0
PCICO_PTM1
BAR Ox17-0x14 RIW RIW
PCI PTM
1 BAR
PCICO_PTM2BAR
Ox1
B-Ox18 RIW RIW PCI PTM 2 BAR
PCICO_ BAR3 Ox1F-Ox1C
- -
PCI Reserved BAR 3
PCICO_ BAR4 Ox23-0x20
-
-
PCI Reserved BAR 4
PCICO_ BAR5 Ox24-0x27
- -
PCI Reserved BAR 5
PCICO_CISPTR Ox2B-Ox28
- -
Unused Cardbus CIS Pointer
PCICO_SBSYSVID
Ox2D-Ox2C
RIW R
PCI Subsystem Vendor ID
PCICO_SBSYSID
Ox2F-Ox2E
RIW R
PCI Subsystem ID
PCICO_EROMBA
Ox33-0x30
- -
Unused Expansion ROM Base Address
PCICO_CAP
Ox34
R R
PCI Capabilities Pointer
PCICO_INTLN
Ox3C
RIW RIW
PCI
Interrupt Line
PCICO_INTPN
Ox3D
R R
PCI Interrupt Pin
PCICO_MINGNT
Ox3E
R R PCI Minimum Grant
Preliminary
Programming
Model
3-25