the loop is executed except the last, so it is best if the branch is predicted taken. The branch target is
the beginning of the
loop, so the branch displacement is negative and s = 1.
If branch displacements are positive
(s
= 0), the branch is predicted not taken. If the branch
instruction is any form of
bclr
or
beetr
except the "branch always" forms, then s = 0, and the branch is
predicted not taken.
There is a
peculiar consequence
of
this prediction algorithm for the absolute forms
of
be
(bea and
bela). As described in "Unconditional 8ranch Target Addressing Options" on page 3-34, if the
algebraic sign of the displacement is negative
(s
= 1), the branch target address is in high memory. If
the algebraic sign of the displacement is positive (s = 0), the branch target address is in low memory.
8ecause these are absolute-addressing forms, there is no reason to treat high and
low memory
differently. Nevertheless, for the high memory case the
default prediction is taken, and for the low
memory case the default prediction is not taken.
80[4]
is the prediction reversal bit. If
80[4]
= 0, the default prediction is applied. If
80[4]
= 1, the
reverse
of
the standard prediction is applied. For the cases in Table 3-17 where
80[4]
=
Y,
software
can reverse the
default prediction. This should only be done when the default prediction is likely to be
wrong. Note that for the
"branch always" condition, reversal of the default prediction is not allowed.
The PowerPC Architecture requires assemblers to provide a way to conveniently control branch
prediction. For any conditional branch mnemonic, a suffix may be added to the mnemonic to
control
prediction, as follows:
+ Predict branch to be taken
Predict branch to be not taken
For
example,
beetr+
causes
80[4]
to be set appropriately to force the branch to be predicted !aken.
3.8 Speculative Accesses
The PowerPC Architecture permits implementations to perform speculative accesses to memory,
either for instruction fetching,
or
for data loads. A speculative access is defined as any access which
is not required by a
sequential execution model.
For example, prefetching instructions beyond an undetermined conditional branch is a speculative
fetch; if the branch is not in the predicted direction, the program,
as
executed, never needs the
instructions from the predicted path.
Sometimes speculative accesses are inappropriate. For
example, attempting to fetch instructions
from addresses that cannot contain instructions can cause problems.To protect against errant
accesses to
"sensitive" memory or I/O devices, the PowerPC Architecture provides the G (guarded)
storage attribute, which can be used to specify
memory
pages from which speculative accesses are
prohibited.
(Actually, speculative accesses to guarded storage are allowed in certain limited
circumstances; if an instruction in a cache block will be executed, the rest of the cache block can be
speculatively accessed.)
3.8.1 Speculative Accesses in
the
PPC405GP
The PPC405GP does not perform speculative loads.
Preliminary Programming Model
3-37
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