The compression software stores compressed and uncompressed instructions
in
64-byte blocks,
called
compression blocks. The number of bytes used to store compressed code varies in each
compression
block, depending on the encoding. Because the length resulting compressed block
varies, the compression software generates an index ,table that translates addresses of
uncompressed 64-byte
blocks, called target instruction addresses (TIAs), to addresses of the
compressed
variable length blocks. The index table also contains information indicating, for each
block, whether the compression block was compressed
or
left uncompressed. The index table is
loaded into system memory with the compressed blocks of program code. The decompression
controller accesses the index table when a fetch is made to compressed program space.
14.1.2 Code Decompression
The decompression controller is located between the processor core and the SDRAM and EBC
memory
controllers, isolating the memory controllers from the processor local bus (PLB). The
decompression
controller is transparent to the processor core and the memory controllers. The
processor core side of the decompression
controller is a PLB slave to the PLB bus, and the memory
controller side is a PLB master to the memory controllers. Instruction-side requests for external
memory go though the decompression controller, and are either intercepted for decompression
or
allowed to pass through unaltered.
The decompression controller must distinguish between compressed and uncompressed code space.
To
accomplish this, the processor core provides a signal with each instruction memory reference,
indicating whether the reference is
in
compressed
or
uncompressed memory space. The CPU's
UO
storage attribute is used to implement this signal. When address translation is enabled (the IR field of
the Machine State Register (MSR) is 1), a corresponding
UO
bit is implemented
in
translation
lookaside
buffer (TLB) entries
in
the memory management unit (MMU). When address translation is
disabled (MSR[IR] = 0, the Storage User-defined 0 Register (SUOR) implements the
UO
storage
attribute for memory regions. The
UO
storage attribute indicates whether a page is marked as
compressed.
14.1.3 Instruction Fetches to Compressed Pages
The decompression controller intercepts instruction fetches to code
in
uncompressed pages, locates
the compressed code
in
memory, and decompresses the instruction stream before forwarding it to the
processor core. These steps are detailed
in
the following procedure:
1. Locate compressed code
a.
Calculate offset into index table.
b.
Retrieve index from index table.
c.
Calculate address of compression block using the index table entry.
d. Retrieve compression
block.
2. Decode instructions into the output buffer, if required.
3. Return instructions to the processor core.
The decompression
controller contains a 64B output buffer that stores instruction words as they are
decompressed. Because code is compressed and decompressed
in
64B blocks and the CPU
requests
smaller line fills (32 bytes), some accesses to compressed instructions may already be
available
in
the decompression controller output buffer, decompressed and ready for execution.
In
this
case,
line fill requests are serviced from the output buffer, without having to address external memory.
14-2
PPC405GP User's Manual Preliminary
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