The following status bits are set:
1.
If the bridge PCI target executes a target abort, PCICO_STATUS[STA] =
1.
The setting of
PCICO_STATUS[STA] in such an event is non-maskable. Writing a 1 to PCICO_STATUS[STA]
clears the field.
2.
f the bridge PCI target asserts PCISErr, PCICO_STATUS[SSE] =
1.
The setting of
PCICO_STATUS[SSE] is non-maskable. Writing a 1 to PCICO_STATUS[SSE] clears the field.
3.
If the bridge PCI target asserts PCISErr, PCICO_ERRSTS[SARME] = 1 to indicate that the bridge
PCI target asserted PCISErr
in
response to a received PLB bus error signal. The setting of
PCICO_ERRSTS[SARME] is non-maskable. Writing a 1 to PCICO_ERRSTS[SARME] clears the
field.
4.
PCICO_ERRSTS[MED] = 1 to indicate that the bridge PLB master received a PLB bus error signal.
Setting of PCICO_ERRSTS[MED] is non-maskable. Writing a 1 to PCICO_ERRSTS[MED] clears
the field.
17.7 PCI Bridge Clocking Configuration
See "PCI Clocking" on page 7-7 for detailed information regarding the choice and setup involved with
both synchronous and asynchronous
PCI clocking modes.
17.8 PCI Power Management Interface
The PCI bridge supports PCI Power Management Interface Specification Revision
1.1
(PCI-PM).
17.8.1 Capabilities and Power Management Status and Control Registers
The PCI bridge has a capabilities structure
in
the PCI configuration space that indicates that the PCI
bridge core is PCI Power Management capable. The capabilities structure includes the following
registers:
• PCICO_CAPID, value
Ox01,
indicates Power Management
• PCICO_NEXTIPTR, points to next capabilities structure
• PCICO_PMC, value Ox0202, indicates no specific capabilities
• PCICO_PMCSR, indicates hold the current PowerState
• PCICO_PMCSR_BSE, value
OxOO,
unused in PCI-to-PCI bridge
• PCICO_Data, value
OxOO,
not used
• See "PCI Configuration Registers" on page 17-29 for details.
17.8.2 Power State Control
The current power management state is reported by reading PCICO_PMCSR. The PCI bridge
supports states
DO,
D1, D3hot, and D3cold. State D2 is not supported. When the state is not
DO,
the
PCI bridge is masked from being a master
or
a memory
or
I/O target on the
PCI
bus. The PCI bridge
can
still be a config target. Thus, accesses claimed by the PCI bridge when in state
DO
are no longer
claimed, resulting
in
master aborts on the PLB
or
PCI if such an access is attempted. Note that this
mask is independent of the state of the
PCI Command register.
Preliminary PCI Interface
17-59
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