IBM PowerPC 405GP User Manual

12.9.6 Debug Events
Debug events, enabled and configured by DBCRO and DBCR1 and recorded in the DBSR, cause
debug operations. A debug event occurs when an event
listed in Table 12-4, "Debug Events," on
page 12-16 is detected. The debug operation is performed after the debug event.
In internal debug mode, the processor generates a debug interrupt when a debug event occurs. In
external debug mode, the processor stops when a debug event occurs. When internal and external
debug mode are both enabled, the processor stops on a debug event with the debug interrupt
pending. When external and internal debug mode are both disabled, and debug wait mode is enabled
the processor stops, but can be restarted by an interrupt. When all debug modes are disabled, debug
events are recorded in the DBSR, but no action is taken.
Table 12-4 lists the debug events and the related fields in DBCRO, DBCR1, and DBSR.
DBCRO and
DBCR1 enable the debugs events, and the DBSR fields report their occurrence.
Table 12-4. Debug Events
Enabling
DBCRO, DBCR1 Reporting
Event Fields DBSR Fields
Description
Instruction Completion IC IC
Occurs after completion of an instruction.
Branch Taken
BT
BT
Occurs before execution of a branch
instruction determined to be taken.
Exception Taken EDE EXC
Occurs after an exception.
Trap
Instruction TDE
TIE
Occurs before execution of a trap
instruction where the conditions are such
that the trap will occur.
Unconditional UDE UDE Occurs immediately upon being set by the
JTAG debug port.
Instruction Address IA 1, IA2, IA3, IA 1, IA2, IA3,
Occurs before execution of an instruction
Compare
IA4,IA12,
IA4
at an address that matches an address
IA12X,IA12T,
defined by the Instruction Address
IA34, IA34X,
Compare Registers (lAC1-IAC4).
IA34T
Data Address D1R, D1W, D1S, DR2,DW2 Occurs before execution of an instruction
Compare
D2R, D2W,
D2S,
that accesses a data address that matches
DA12,DA12X
the contents of the specified
DAC register.
Data Value Compare
DV1M, DV2M, DR1, DW1
Occurs after execution of an instruction
DV1BE,DV2BE
that accesses a data address for which a
DAC occurs, and for which the value at the
address matches the value
in the specified
DVC register.
Imprecise IDE Indicates that another debug event
occurred while MSR[DE]
= 0
1'2.9.7 Instruction Complete Debug Event
This debug event occurs after the completion of an instruction. If DBCRO[IDM] = 1, DBCRO[EDM] = 0
and MSR[DE] =0 this debug event is disabled.
12-16 PPC405GP User's Manual Preliminary

IBM PowerPC 405GP Specifications

General

Brand	IBM
Model	PowerPC 405GP
Category	Computer Hardware
Language	English