Chapter
2.
On-Chip Buses
The on-chip bus architecture, which consists of the processor local bus (PLB), on-chip peripheral bus
(OPB), and device control register (OCR) bus, provides a link between the cache units
in
the
processor core and other PLB and
OPB master and slave devices used
in
the PPC405GP. These
devices
include the SDRAM controller, PCI bridge, DMA controller, and external bus controller.
The PLB is a high performance bus used to access memory through bus interface units. The PLB
master and
slave assignments for the PPC405GP are listed in "PLB Masters and Slaves" on
page 2-2.
Lower performance
peripherals (such as serial ports) are attached to the OPB. A bridge between the
PLB and
OPB enables data transfers between PLB masters and OPB slaves. DMA peripherals can
also be OPB peripherals.
The OCR bus is used primarily to access status and control registers of the various PLB and OPB
masters and slaves. The OCR bus offloads status and control read and write transfers from the PLB.
The
OCR bus is not described further
in
this chapter.
The
following publications, which are available from your IBM representative and in the IBM
Microelectronics technical library (www.chips.ibm.com). describe the on-chip bus architecture:
• The CoreConnectr
M
Bus Architecture
• Processor Local Bus Architecture Specifications
• On-Chip Peripheral Bus Architecture Specifications
• Device Control Register Bus Architecture Specifications
The PPC405GP
block diagram (Figure
1-1
on page 1-2) illustrates the on-chip bus structure of the
PPC405GP.
2.1
Processor Local Bus
The PLB is a high-performance on-chip bus. The PLB supports read and write data transfers between
master and
slave devices equipped with a PLB interface and connected through PLB signals.
Each PLB master is attached to the PLB through separate address, read data and write data buses,
and transfer
qualifier signals. PLB slaves are attached to the PLB through shared, but decoupled,
address, read data and write data buses, and transfer control and status signals for each data bus.
Access to the PLB is granted through a
central arbitration mechanism that enables masters to
compete for bus ownership. This arbitration mechanism provides for fixed and fair priority schemes.
Timing
for all PLB signals is provided by a clock source that is shared by all PLB masters and slaves.
Preliminary On-Chip Buses 2-1
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