16.4.4 Device-Paced Burst Write Transfer
Figure 16-10 shows the peripheral interface timing for a device-paced burst write transfer to a burst
enabled (EBCO_BnAP[BME]=1) bank. The transaction begins with the address being driven.
PerCSn
then becomes active EBCO_BnAP[CSN] cycles after the address. At this point the signalling
sequence depends on whether or not byte enable mode is enabled for the bank.
• If byte enable mode is disabled (EBCO_BnAP[BEM]=O) PerWBEO:3 are write byte enables. In this
case the appropriate write byte enables go
low EBCO_BnAP[WBN] cycles after PerCSn becomes
active for the first element in a burst and EBCO_BnAP[WBN] cycles after each new address for the
remainder of the burst.
If
EBCO_BnAP[WBN]<>O, PerWBEO:3 is driven inactive on the same
PerClk edge that write data is transferred (see below). Otherwise, PerWBEO:3 remains
low for all
data elements in the burst.
• If EBCO_BnAP[BEM]=1, PerWBEO:3 are byte enables and have the same timing as PerAddrO:31.
The EBC then waits until EBCO_BnAP[FWT]+ 1 cycles have elapsed since the start of the transaction
and begins
sampling PerReady. If device-paced timeouts are disabled (EBCO_CFG[PTD]=O) the EBC
waits indefinitely for PerReady. Otherwise, the EBC waits only EBCO_CFG[RTC] cycles from the start of
the transaction until logging a timeout error.
If PerReady is sampled active and Sample On Ready is disabled (EBCO_BnAP[SOR]=O) the EBC
waits one more cycle.
At
this point the write transfer occurs and the EBC reads the peripheral error
input, PerErr.
The next address of the burst is then driven and after EBCO_BnAP[BWT]+ 1 cycles the EBC waits for
PerReady as described above. The remaining items in the burst are transferred
in
this same manner,
except that PerBLast is active for the last data element. The EBC then drives
PerCSn, PerOE and
PerBLast high and waits EBCO_BnAP[TH] cycles before
allowing any pending transfers to occur.
External
Bus
Controller 16-15
To Next Page
Loading...
Need help?
General
