4.1
leu
Organization
The
ICU manages instruction transfers between external cachable
memory
and the instruction queue
in the execution unit.
The
ICU.contains a two-way set-associative 16KB cache memory. Each way is organized in 256 lines
of
eight words (eight instructions) each.
As
shown in Table 4-1, tag ways A and B store instruction address bits
AO:21
for each line in cache
ways A
and
B.
Instruction address bits A
19
:
26
serve as the index to the cache array. The two cache
lines that correspond to the same line index (one
in
each way) are called a congruence class.
Table 4-1. Instruction Cache Organization
Tags (Two-way Set)
Instructions
(Two-way Set)
Way A Way 8 Way A Way 8
AO:21
Line 0 A
AO:21
Line 0 B
Line 0 A Line 0 B
AO:21
Line 1 A
AO:21
Line 1 B
Line 1 A
Line 1 B
· · ·
·
· · ·
·
·
· ·
·
AO:21
Line 254 A
AO:21
Line 254 B
Line 254 A Line 254 B
AO:21
Line 255 A
AO:21
Line 255 B
Line 255 A Line 255 B
When
a cache line is to be loaded,
the
cache way to receive the line is determined by using an least-
recently-used (LRU) policy.
The
index, determined by the instruction address, selects a congruence
class. Within a congruence class, the line which was accessed most recently is retained, and the
other
line is marked as LRU, using an LRU bit in the tag array. The line to receive the incoming data is
the
LRU line. After the cache line fill, the LRU bit is then set to identify
as
least-recently-used the line
opposite the line just filled.
4-2
PPC405GP
User's Manual
Preliminary
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