IBM PowerPC 405GP User Manual

31 CWS Cache Way Select
o Cache way is A.
1 Cache way is B.
4.4.1 CCRO Programming Guidelines
Several fields in CCRO affect ICU and DCU operation. Altering these fields while the cache units are
involved in PLS transfers can cause errant operation, including a processor hang.
To guarantee correct ICU and DCU operation, specific code sequences must be followed when
altering CCRO fields.
CCRO[IPP, FWOA] affect ICU operation. When these fields are altered, execution of the following
code sequence (Sequence 1) is required.
! SEQUENCE 1
Altering CCRO[IPP, FWOA]
! Turn off interrupts
mfmsr
RM
addis RZ,rO,Ox0002 ! CE bit
ori
RZ,RZ,Ox8000 ! EE bit
andc
RZ,RM,RZ! Turn off MSR[CE,EE]
mtmsr
RZ
! sync
sync
! Touch code sequence into i-cache
addis RX,rO,seq1 @h
ori RX,RX,seq1 @I
icbt rO,RX
! Call function to alter CCRO bits
b
seq1
back:
! Restore MSR to
original value
mtmsr RM
•
•
•
! The following function must be in cacheable memory
.align 5 ! Align CCRO altering code on a cache line boundary.
seq1:
icbt
rO,RX ! Repeat ICST and execute an ISYNC to guarantee CCRO
isync ! altering code has been completely fetched across the PLB.
mfspr
RN,CCRO ! Read CCRO.
andi/ori RN,RN,OxXXXX ! Execute and/or function to change any CCRO bits.
!
Can use two instructions before having to touch
! in two cache
lines.
Preliminary Cache Operations
4-13

IBM PowerPC 405GP Specifications

General

Brand	IBM
Model	PowerPC 405GP
Category	Computer Hardware
Language	English