01
Figure 17-31.
PCI
Cache Line Size Register (PCICO_CACHELS)
I PCI Cache Line Size
17.5.3.10 PCI
Latency
Timer
Register
(PCICO_LATTIM)
PCICO_LATTIM holds the value of the
PCllatency
timer. The granularity of the latency timer is 8 PCI
cycles.
Therefore, the 3 low-order bits of this register are read-only and return Ox111.
01
Figure 17-32.
PCI
Latency Timer Register
(PCICO_LATTIM)
I PCI Latency Timer
PCI Local Bus Specification Version 2.2 specifies that PCI masters capable of multi-beat bursts must,
after
losing their PCI grant, get off the bus after a number of clock cycles equivalent to the value
in
PCICO_LATTIM.
The actual number of clock cycles to disconnect varies somewhat when
in
asynchronous mode. If
PCICO_LATTIM
is programmed
in
asynchronous mode to a value that is less than 64, the PCI bridge
PCI master interface could timeout, regardless of the state of its grant line.
In
asynchronous mode, the PCI master starts its timer and can timeout regardless of the state of the
PCI grant. This is strictly a performance issue and does not limit functionality or affect data integrity.
Several factors affect the frequency of timeouts.
• The amount of PCI bus traffic.
In
moderate to heavily loaded systems, this is less of an issue
because a
PCI master tends to lose its grant more often after gaining the
.bus.
• Fast targets that introduce few or no wait states reduce the chances of timeouts occurring.
17.5.3.11 PCI
Header
Type
Register
(PCICO_HDTYPE)
PCICO_HDTYPE (bits 0:6) identifies the second part of the PCI header, which begins at offset
Ox1
o.
It
also
determines whether a device contains multiple functions (bit 7). The PCI bridge implements the
17-36
PPC405GP User's Manual
Preliminary
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