IBM PowerPC 405GP User Manual

01
Figure 17-29. PCI Revision 10 Register (PCICO_REVIO)
Revision 10 Revision level of device.
17.5.3.8 PCI Class Register (PCICO_CLS)
This register holds the class code. This register is Ox060000 at reset, which indicates that the PCI
bridge is a bridge device located between the PLB and the PCI bus; however, the local CPU (PLB
master) can write a
value to this register for the case where PCI bridge is not the host bridge.
Class information is defined in the PCI Local Bus Specification, Version 2.2.
BASE
INT
1
2
3
=*
16
1
1
5
=*
01
t
SUB
Figure 17-30. PCI Class Register (PCICO_PCICLS)
23:16 BASE Base Class Reset to Ox06, which indicates bridge
device.
Users of the
RISCWatch debugger must
use the
PCICO_BASECC register to
access this
field.
15:8
SUB Subclass
Reset to 00, which indicates host bridge.
Users of the
RISCWatch debugger must
use the
PCICO_SUBCLS register to
access this
field.
7:0 INT
Interface Class
Reset to 00.
Users of the RISCWatch debugger must
use the
PCICO_INTCLS register to access
this
field.
17.5.3.9 PCI Cache Line Size Register (PCICO_CACHELS)
PCICO_CACHELS determines the size of a PCI cache line. PCI bridge does not support a PCI cache.
Therefore, this register is
read-only and returns OxOO when read.
Preliminary PCI Interface 17-35

IBM PowerPC 405GP Specifications

General

Brand	IBM
Model	PowerPC 405GP
Category	Computer Hardware
Language	English