4 A1P DMAAck1 Polarity
o DMAAck1 is active high
1 DMAAck1 is active low
5
E1P
EOT1[TC1] Polarity
o
EOT1
[TC1] is active high
1
EOT1[TC1] is active low
6
R2P DMAReq2 Polarity
o DMAReq2 is active high
1 DMAReq2 is active low
7 A2P
DMAAck2 Polarity
o DMAAck2 is active high
1 DMAAck2 is active low
8 E2P EOT2[TC2] Polarity
o EOT2[TC2] is active high
1
EOT2[TC2] is active low
9 R3P
DMAReq3 Polarity
o DMAReq3 is active high
1 DMAReq3 is active low
10
A3P DMAAck3 Polarity
o DMAAck3 is active high
1 DMAAck3 is active low
11
E3P EOT3[TC3] Polarity
o EOT3[TC3] is active high
1 EOT3[TC3] is active low
12:31
'.
•
.....
Reserved
18.3.2 DMA Sleep Mode Register (DMAO_SLP)
The Sleep Mode Register (DMAO_SLP) enables the DMA controller to enter sleep (low-power) mode
and programs the number of PLB clock cycles to wait when the controller is idle before going to sleep.
The DMA controller only goes to sleep when no DMA channels are enabled and no configuration or
status (DCR) register operations are
in
progress. Reading
or
writing any of the DMA control or status
register awakens the
~MA
controller.
To
enable sleep mode set DMAO_SLP[SME] and CPMO_ER[DMA]. When sleep mode is enabled and
the DMA controller becomes idle the
10-bit idle timer begins counting down from the programmed
value.
Only the upper 5 bits of the idle counter are programmable; the lower 5 bits are hardcoded to
Ob11111. Therefore, the minimum granularity of the idle timer is 32 PLB clock cycles. When the
counter reaches zero, the controller
is placed
in
sleep mode.
18-6
PPC405GP User's Manual Preliminary
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