Figure 12-12 shows the range selected
in
an inclusive DAC range address compare. Note that the
address
in
DAC1
is considered part of the range, but the address
in
DAC2 is not, as shown
in
the
preceding
examples. The thick lines indicate that the indicated address is included
in
the compare
results.
o
FFFF FFFF
I
DAC1
DAC2
Figure 12-12. Inclusive
DAC
Range Address Compares
Figure 12-13 shows the range selected
in
an exclusive DAC range address compare. Note that the
address in
DAC1
is not considered part of the range, but the address
in
DAC2 is, along with the
highest memory address, as shown in the preceding
examples.
o
FFFF
FFFF
I
DAC1
DAC2
Figure 12-13. Exclusive
DAC
Range Address Compares
The
DAC
Compare Size fields (DBCR1
[D1
S,
D2S]) are not used by DAC range comparisons.
12.9.13.3 Data Address Compare (DAC) Applied
to
Cache Instructions
Some cache instructions may cause DAC debug events. There are several special cases.
Table 12-5 summarizes possible DAC debug events by cache instruction:
Table 12-5.
DAC
Applied
to
Cache Instructions
Possible DAC Debug Event
Instruction
DAC-Read DAC-Wrlte
dcba
No
Yes
dcbf
No
Yes
dcbl
No
Yes
dcbst
No
Yes
dcbt
Yes
No
dcbz
No
Yes
dccci
No
No
dcread
No
No
dcbtst
Yes
No
Icbl
Yes
No
12-20
PPC405GP User's Manual Preliminary
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