IBM PowerPC 405GP User Manual

Table 7·5. Possible Clocking Ratios for Reference Clock of 41.SMHz
Strapping Options Calculated Values (MHz)
FWD
CPu/PLB FBK
M
VCO CPU PLB
By-pass
2
1 x
-
-
refclk refclk
2
x
- -
refclk
refclkl2
3
x
- -
refclk refclkl3
4
x
-
-
refclk refclkl4
3
2 2 12
500 166 83
3
2
3
18
750 250
125
3 3 2 18
750 250 83
3 4 1 12
500
166 41
4
1 3
12
500
125 125
4 2 2 16 666 166 83
4
3 1 12 500
125 41
4 4 1 16 666 166 41
6 1 2 12 500 83 83
6 1 3
18
750 125 125
6
2
1
12
500
83 41
6 3
1 18
750 125 41
Note 1: x = don't care.
Note 2: By-pass mode is designed for hardware emulator use only.
Contact your IBM representative for more information.
Note 3: Not all PPC405GP parts support the frequencies shown. Check
PPC405GP Datasheetfor supported CPU and PLB frequencies for
a specific part number.
7.5 PCI Clocking
The PPC405GP PCI interface can run synchronously or asynchronously relative to the on-chip PLB.
The state at reset of the PCI Asynchronous Mode Enable (PAME) strapping pin selects synchronous
PCI mode or asynchronous PCI mode. The state of the PAME pin is reported in the PAME field of the
CPCO_PSR. For information about the strapping pins, refer to PowerPC 405GP Embedded
Processor Data
Sheet, which is available from your IBM representative and in the Technical Library
on the IBM Microelectronics web site (www.chips.ibm.com).
Lower PCI latency through the PCI logic occurs in synchronous PCI mode, which should be used for
host-bridge applications in which the PCI bus frequency is less than or equal to 33 Mhz, and the PLB
frequency is an integer multiple of the PCI frequency. PPC405GP applications for higher PCI
frequencies, or for PCI adapters, should use asynchronous PCI mode.
Preliminary Clocking
7·7

IBM PowerPC 405GP Specifications

General

Brand	IBM
Model	PowerPC 405GP
Category	Computer Hardware
Language	English