IBM PowerPC 405GP User Manual

The SDRAM controller maintains the SDRAM in self-refresh mode, independent of any pending
memory access requests, until SDRAMO_CFG[SRE] is cleared. Any attempt to read or write SDRAM
memory during this time will stall the PLB ..
Once SDRAMO_CFG[SRE] is cleared, the SDRAM controller performs the following:
1. Exits self-refresh mode.
2. Performs an auto-refresh cycle.
3. Clears SDRAMO_STATUS[SRSTATUS].
The SDRAM controller is then ready to service any memory request.
15.6 Power Management
The SDRAM controller provides a sleep mode where all SDRAM controller clocking is disabled with
the exception of the SDRAM refresh logic and the power management wake-up logic. When the
SDRAM controller is in sleep mode SDRAM refresh continues to preserve the contents of the
memory and maintain the refresh interval.
15.6.1 Sleep Mode Entry
Sleep mode is enabled by setting SDRAMO_CFG[PME] and CPMO_ER[SDRAM]. Once sleep mode
is enabled and the SDRAM controller has been idle for the number of cycles programmed in
SDRAMO_PMIT, the SDRAM controller goes to sleep.
15.6.2 Power Management Idle Timer (SDRAMO_PMIT)
The SDRAMO...;.PMIT register determines the number for SDRAM clock (MemClkOut1 :0) cycles that
the controller must be idle before it asserts a sleep request when power management is enabled
(SDRAMO_CFG[PME]=1). At system reset, SDRAMO_PMIT[CNT] is set to zero. This corresponds to
a sleep request after 32 idle cycles.
CNT
+
1
0
415
t
9110
311
11111
Figure 15-17. Power Management Idle Timer (SDRAMO_PMIT)
0:4 CNT Count
0-31
5:9 Always Ob11111
10:31
••••••••••••••••••••••••••••••••••••••
Reserved
15-20
PPC405GP User's Manual Preliminary

IBM PowerPC 405GP Specifications

General

Brand	IBM
Model	PowerPC 405GP
Category	Computer Hardware
Language	English