17.5.3.35 PCI Data Register (PCICO_DATA)
PCICO_DATA is
an
optional
register
that
provides a
mechanism
for
the
function
to
report
state
dependent
operating
data
such
as
power
consumed
or
heat
dissipation.
The
PCI
bridge
does
not
implement
this register; therefore, it returns °
when
this
register
is read.
01
Figure 17-56.
PCI
Data (PCICO_DATA)
I
PCI
Data
17.5.3.36
Bridge
Options
2 Register (PCICO_BRDGOPT2)
PCICO_BRDGOPT2
controls
various
operating
parameters
of
the PCI bridge.
DPR
PTDT
t
+
31
2
11101
t f t
EWPCI PSTLTD
HCE
Figure 17-57. Bridge Options 2 Register (PCICO_BRDGOPT2)
15:14
"
......
,
Reserved
J
",
13
EWPCI
External
Write to PCI Command Interrupt Software can also set or clear this bit.
o
No
write to PCICO_CMD has occurred.
1
External
PCI
master has written to
PCICO_CMD.
12
DPR
Drive PCI Reset Software that asserts this bit must leave is
o Normal operation asserted long enough to guarantee the
1 Causes
PCIReset
pin to be asserted.
PCI
pulse width requirements. DPR does
not reset
PLB
bus interface registers or
PCI
bridge registers.
PCIReset
is also asserted when the
PCI
bridge is reset.
11
:8
PSSTLD
Subsequent Target Latency Timer Duration Only set
on
reads.
Specifies the number of
PCI
clocks that a
In
synchronous mode, PSSLTD equals the
PCI master burst can be held
in
a wait
maximum number of
PCI
clocks to
state before a target disconnect is initiated. disconnect.
In
asynchronous mode,
PSSLTD plus 3 equals the maximum
number of
PCI
clocks to disconnect. The
asynchronous
value must be 2 or less.
17-52
PPC405GP User's Manual Preliminary
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