IBM PowerPC 405GP

7:3 Reserved
2
PTDT PCI Discard Timer Disable When enabled, the PCI bridge never
o Disabled
discards delayed read data.
1
Enabled
1 Reserved
0
HCE Host Configuration Enable HCE controls host PCI access to the PCI
o Disabled
bridge configuration registers. All host
1
Enabled
attempts to access the PCI bridge PCI
configuration registers are retried. This
give the
local CPU (PLB master) time to
initialize them before the host sees them.
In synchronous mode, the PCI subsequent target latency timer duration equals the maximum number
of
PCI clocks to disconnect. In asynchronous mode, PCI subsequent target latency timer duration
plus 3 equals the maximum number of
PCI clocks to disconnect. The asynchronous value must be 2
or less.
Preliminary
PCI Interface 17-53