IBM PowerPC 405GP User Manual

11.1 Time Base
The PPC405GP implements a 64-bit time base as required in The PowerPC Architecture. The time
base, which increments once during each period of the source
clock, provides a time reference. The
source
clock is either the CPU clock or an external clock connected to the TmrClk input. The CETE
field of Chip Control Register 1 (CPCO_CR1 [CETE]) selects the clock source.
Read access to the time base is through the
mftb instruction. mftb provides user-mode read-only
access to the time base. The TBR numbers (Ox10C and Ox10D; TBL and TBU, respectively) that
specify the time base registers to
mftb are not SPR numbers. However, the PowerPC Architecture
allows an implementation to handle mftb as mfspr. Accordingly, these register numbers cannot be
used for other
SPRs. PowerPC compilers cannot use mftb with register numbers other than those
specified
in the PowerPC Architecture as read-access time base registers (Ox10C and Ox10D).
Write access to the time base, using mtspr, is privileged. Different register numbers are used for read
access and write access. Writing the time base is
accomplished by using SPR Ox11 C and SPR
Ox11 D (TBL and TBU, respectively) as operands for mtspr.
The period of the 64-bit time base is approximately 2925 years for a 200 MHz clock source. The time
base does not generate interrupts, even when it wraps. For most
applications, the time base is set
once at system reset and
only read thereafter. Note that the FIT and the watchdog timer (discussed
below) are driven by O~ 1 transitions of bits from the TBL. Transitions caused by software alteration of
TBL have the same effect as transitions caused by
normal incrementing of the time base.
Figure 11-2 illustrates the TBL.
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0
Figure 11-2. Time Base lower (TBl)
Time Base Lower
11-2
PPC405GP User's Manual
Current count; low-order 32 bits of time
base.
Preliminary
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IBM PowerPC 405GP Specifications

General

Brand	IBM
Model	PowerPC 405GP
Category	Computer Hardware
Language	English