IBM PowerPC 405GP User Manual

PCI bridge is also a PCI target for configuration cycles when its PCIIDSel pin is active. PCI bridge will
master abort if a configuration
cycle is run to itself.
Table 17-6. Transaction Mapping: PCI ~ PLB
PCI Transaction PLB Transaction
PCI Master ~ Bridge (PCI Target
Bridge Mapping
Bridge (PLB Master Interface) ~ PLB
Interface}
and Qualifications Slave
Single-Beat
Memory Read PCI address decodes a-byte/doubleword read
to PTM1/BAR1 or
PTM2/BAR2, memory
access
flag
Burst Memory Read
PCI address decodes
a-byte/doubleword read
to PTM1/BAR1 or
PTM2/BAR2, memory
access
flag
Memory Read Line
PCI address decodes
Doubleword burst read
to PTM1/BAR1 or
PTM2/BAR2, memory
access
flag
Memory Read Multiple
PCI
address decodes Doubleword burst read
to PTM 1 /BAR 1 or
PTM2/BAR2, memory
access
flag
Memory Read PCI address decodes Doubleword burst read
to PTM1/BAR1 or
PTM2/BAR2, memory
access flag
Single-Beat Memory Write PCI address decodes 1 ~ a-byte write
to PTM1/BAR1 or
PTM2/BAR2, memory
access
flag
Single-Beat
Memory Write and Invalidate
PCI
address decodes
1
~ a-byte write
to PTM 1 /BAR 1 or
PTM2/BAR2, memory
access
flag
Burst Memory Write
PCI address decodes
Word burst write
to PTM1/BAR1 or
PTM2/BAR2, memory
access
flag
Burst Memory Write and Invalidate
PCI
address decodes
Word burst write
to PTM1/BAR1 or
PTM2/BAR2, memory
access
flag
-
Not supported Memory line reads
-
Not supported Memory line writes
17.4.2.1 PLB Master Commands
PCI bridge generates PLB transactions based on the type and length of received PCI transactions.
The
following sections describe the transaction types supported and outline the translation of
commands from one bus to the other.
17-14
PPC405GP User's Manual Preliminary

IBM PowerPC 405GP Specifications

General

Brand	IBM
Model	PowerPC 405GP
Category	Computer Hardware
Language	English