IBM PowerPC 405GP

12.7 Processor Control
The PPC405GP provides the following debug functions for processor control. Not all facilities are
available
in all debug modes.
Instruction Step The processor is stepped one instruction at a time, while stopped, using the
JTAG debug port.
Instruction Stuff While the processor is stopped, instructions can be stuffed into the processor
and executed using the
JTAG debug port.
Halt The processor can be stopped by activating
an external halt signal on an
external event, such as a logic analyzer trigger. This signal freezes the
processor
architecturally. While frozen, normal instruction execution stops and
architected processor resources can be accessed and altered using the
JTAG
debug port. Normal execution resumes when the halt signal is deactivated.
Stop The processor can be stopped using the JTAG debug port. Activating a stop
causes the processor to become
architecturally frozen. While frozen, normal
instruction execution stops and the architected processor resources can be
accessed and altered using the
JTAG debug port.
Reset
An external reset signal, the JTAG debug port, or DBCRO can request core,
chip, and system resets.
Debug Events A debug event triggers a debug operation. The operation depends on the
debug mode. For more information and a list of debug events, see
"Debug
Events"
on page 12-16.
Freeze Timers The
JTAG debug port or DBCRO can control timer resources. The timers can
be enabled to run, freeze always, or freeze on a debug event.
Trap
Instructions The trap instructions tw and twi can be used, with debug events, to implement
software breakpoints.
12.8 Processor Status
The processor execution status, exception status, and most recent reset can be monitored.
Execution Status The
JTAG debug port can monitor processor execution status to determine
whether the processor is stopped, waiting, or running.
Exception Status The
JTAG debug port can monitor the status of pending synchronous
exceptions. .
Most Recent Reset The JTAG debug port or an mfspr instruction can be used to read the Debug
Status Register (DBSR) to determine the type of the most recent reset.
12.9 Debug Registers
Several debug registers, available to debug tools running on the processor, are not intended for use
by application code. Debug tools control debug resources such
as debug events. Application code
that uses debug resources can cause the debug tools
to fail, as well as other unexpected results,
such
as program hangs and processor resets.
Application code should not use the debug resources, including the debug registers.
12-8
PPC405GP User's Manual Preliminary