The local CPU must update the following registers (if the default value is not suitable or they were not
strapped to appropriate
values at reset) before setting the Host Config Enable bit:
• The address map registers (see "Address Map Initialization" on page 17-61)
• PCICO_ VENDID
• PCICO_DEVID
• PCICO_REVID
• PCICO_CLS
• PCICO_SBSYSID
• PCICO_SBSYSVID
17.9.4 Local Processor
Boot
from
PCI
Memory
The PCI bridge has a mode that enables a PLB master to access a PCI memory range without initial
configuration cycles. This mode is enabled when CPCO_PSR[RL] =
1.
System designers can use this
mode to
enablea processor to access a boot ROM
in
PCI memory space.
The
PCI bridge comes out of reset with
PMMO
enabled and programmed for the address range,
OxFFFEOOOO-OxFFFFFFFF. Also, PCICO_CMD[ME] = 1 after reset. Note that enabling PCI boot
mode does not prevent subsequent updates to the
PMMO
registers.
Note:
The PPC405GP allows booting from PCI memory. See Chapter
9,
"Pin Strapping and Sharing"
for more information.
17.9.5 Type 0 Configuration Cycles
for
Other Devices
Twenty-one devices can be accessed using the PCIIDSel mechanism. The PCI master asserts 1 bit
of AD(31 :11) for type
0 configuration cycles based
on
the value in the Device Number field. The
mapping is as
follows:
• If
device number is
1,
AD(11) is asserted
• If device number is
2,
AD(12) is asserted
• If device number is 21, AD(31) is asserted
If device number
c~ntains
a value of
22-31,
no bit of AD(31 :11) is asserted.
17.10 Timing Diagrams
This section contains timing diagrams of several different PCI bridge operations. The following
paragraphs describe each diagram
in
detail. Each description assumes basic knowledge of PCI and
PLB
protocols.
Each operation is shown in both synchronous and asynchronous modes. The PCI is clocked at
33 MHz
in
synchronous mode and
66
MHz in asynchronous mode. The PLB is clocked at 100 MHz
in
all cases.
17-64
PPC405GP User's Manual
Preliminary
To Next Page
Loading...
Need help?
General
