For non-cachable memory and for loads misses when CCRO[LWOA] =
1,
the load word as line (LWL)
field in the
CCRO
affects whether load misses are satisfied with a word, or with eight words (the
equivalent of a cache line) of data. If CCRO[LWL] =
0,
only the target word is bypassed to the core. If
CCRO[LWL] =
1,
the DCU saves eight words (one of which is the target word)
in
the fill buffer and
bypasses the target data to the core to satisfy the
load word request. The fill buffer is not written to the
data cache array.
Setting CCRO[LWL]
= 1 provides the fastest accesses to sequential non-cachable memory .
. Subsequent loads from the same line are bypassed to the core from the fill buffer and do not result
in
additional external memory accesses. The load data remains valid in the fill buffer until one of the
following occurs: the beginning of a subsequent load that requires the fill buffer, a store to the target
address, a
debi
or
deeei instruction issued to the target address, or the execution of a
syne
instruction. Non-cachable loads to guarded storage never cause a line transfer on the PLB even if
CCRO[LWL]
= 1. Subsequent loads to the same non-cachable storage are always requested again
from the PLB.
For
cachable memory, the store without allocate (SWOA) field of the
CCRO
controls the type of store
resulting from a store miss. If CCRO[SWOA] =
0,
a store miss causes a line fill. If CCRO[SWOA] =
1,
store misses do not result
in
a line fill, but
in
a single word store to external memory.
4.2.4 Data Cachability Control
When data address translation is disabled (MSR[DR] = 0), data cachability is controlled by the Data
Cache
Cachability Register (DCCR). Each bit
in
the DCCR (DCCR[SO:S31]) controls the cachability
of a 128MB region (see "Real-mode Storage Attribute Control" on page 6-17). If DCCR[Sn] =
1,
caching is enabled for the specified region; otherwise, caching is inhibited.
When data address
translation is enabled (MSR[DR] = 1), data cachability is controlled by the I bit
in
the TLB entry for the memory page. If TLB_entry[l] = 1 , caching is inhibited; otherwise caching is
enabled. Cachability is controlled separately for each page, which can range
in
size from 1 KB to
16MB.
"Translation Lookaside Buffer (TLB)" on page 6-2 describes the TLB.
Programming
Note:
The PowerPC Architecture does not support memory models
in
which
write-through is
enabled and caching is inhibited.
The performance of the PPC405GP is
significantly lower while accessing memory
in
cache-inhibited
regions.
Following system reset, address translation is disabled and all DCCR bits are reset to 0 so that no
memory regions are
cachable. The deeei instruction must execute 128before regions can be
designated as
cachable. This invalidates all congruence classes before enabling the cache. Address
translation can then be enabled, if required, and the TLB
or
the DCCR can then be configured for the
desired
cachability. .
4-8
Programming
~ote:
If a data block corresponding to the effective address (EA) exists
in
the
cache, but the EA is
non-cachable, loads and stores (including debz) to that address are
considered programming errors (the cache
block should previously have been flushed). The only
instructions that can legitimately access such an EA
in
the data cache are the cache
management instructions debf,
debi,
debst,
debt,
debtst,
deeei, and deread.
PPC405GP User's Manual Preliminary
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