instructions drop to the empty queue location closest to the EXU. When there is room in the queue,
Instructions can be returned from the ICU two at a time. If the queue is empty and the ICU is returning
two instructions, one instruction drops into DCD
while the other drops into
PFBO.
PFB1 buffers
ins~ructions
when the pipeline stalls.
Branch instructions are examined in DCD and
PFBO
while all other instructions are decoded
in
DCD.
All instructions must pass through DCD before entering the EXU. The EXU contains the execute,
write-back and
load write-back stages of the pipe. The results of most instructions are calculated
during the execute stage and written to the GPR file during the write back stage. Load instructions
write the GPR
file during the load write-back stage.
Instruction
Queue
ICU
I
PFB1
PFBO
DCD
I
EXU
Fetch
Dispatch
Figure
3-1S.
PPC40SGP Instruction Pipeline
3.7 Branch Processing
The PPC405GP, which provides a variety of conditional and unconditional branching instructions,
uses the branch prediction techniques described in
"Branch Prediction" on page 3-35.
3.7.1
Unconditional Branch Target Addressing Options
The unconditional branches (b, ba, bl, bla) carry the displacement to the branch target address as a
signed 26-bit
value (the 24-bit U field right-extended with
ObOO).
The displacement enables
unconditional
branches to cover an address range of ±32MB.
For the
relative (AA = 0) forms (b, bl), the target address is the current instruction address (CIA, the
address of the branch instruction)
plus the signed displacement.
For the absolute (AA = 1) forms (ba, bla), the target address is 0 plus the Signed displacement.
If
the
sign bit
(U[O]) is
0,
the displacement is the target address. If the sign bit is 1 , the displacement is a
negative
value and wraps to the highest memory addresses. For example, if the displacement is
Ox3FF FFFC (the 26-bit representation of
-4),
the target address is OxFFFF FFFC (0 - 4B, or 4 bytes
below the top of memory).
3-34 PPC405GP User's Manual Preliminary
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