IBM PowerPC 405GP User Manual

2.1.9 OPB Master Assignments
Table 2-1 lists the OPB masters. (The numbering reflects that the PPC405GP implements two
masters; the
OPB can support four masters.)
Table 2-S. PPC40SGP OPB Master Assignments
OPB Agents
Description
DMA controller DMA (master 0)
OPB
to PLB bridge OPB to PLB bridge (master 2)
2.1.10 OPB Arbiter Registers
The OPB arbiter contains the MMIO registers summarized in Table 2-6.
Table 2-6. PLB Arbiter Registers
Mnemonic
Register Name
Address Access
OPBAO_CR
OPB
Arbiter Control Register
OxEF600601
RIW
OPBAO_PR
OPB
Arbiter Priority Register
OxEF600600
RIW
2.1.10.1 OPB Arbiter Control Register (OPBAO_CR)
Page
2-5
2-5
The OPBAO_CR fields controls updating of the OPBAO_PR (described in "OPB Arbiter Priority
Register
(OPBAO_PR)" on page 2-13). Because the PPC405GP provides two masters, master IDs 1
and 3 are ignored.
311
Figure 2-8. OPB Arbiter Control Register (OPBAO_CR)
0 DPE Dynamic Priority Enable
o Dynamic priority disabled
1 Dynamic priority enabled
1 PEN Park Enable
o Park disabled
1 Park enabled
2-12
PPC405GP User's Manual Preliminary

IBM PowerPC 405GP Specifications

General

Brand	IBM
Model	PowerPC 405GP
Category	Computer Hardware
Language	English