IBM PowerPC 405GP

12.9.1 Debug Control Registers
The debug control registers (OBCRO and OBCR1) can enable and configure debug events, reset the
processor,
control timer operation during debug events, enable debug interrupts, and set the
processor debug mode.
12.9.1.1 Debug Control Register 0 (DBCRO)
EOM RST BT TOE IA2 IA 12X IA4 IA34X IA34T
... * * * * * * * *
1
0
1
1
1
2
31415161718191101111121131141151
16
1
17
118
t f t t t t t t
10M Ie EOE IA1 IA12 IA3 IA34 IA12T
3
0
1
31
1
t
FT
Figure 12-4. Debug Control Register 0 (DBCRO)
a EDM External Debug Mode
a Disabled
1 Enabled
1 10M
Internal Debug Mode
a Disabled
1 Enabled
2:3
RST
Reset
Causes a processor reset request when
00 No action set by software.
01 Core reset
10 Chip reset
11 System reset
Attention: Writing 01, 10, or 11 to this field causes a processor reset request.
4
IC
Instruction Completion Debug Event
a Disabled
1 Enabled
5 BT
Branch Taken Debug Event
a Disabled
1 Enabled
6 EDE
Exception Debug Event
a Disabled
1 Enabled
7 TOE
Trap Debug Event
a Disabled
1 Enabled
8 IA1 lAC 1 Debug Event
a Disabled
1 Enabled
9 IA2
lAC
2 Debug Event
a Disabled
1 Enabled
Preliminary
Debugging
12-9