Precise address capture
in
the EBCO_BEAR when a parity error occurs only applies to devices with at
least
one cycle of hold time: EBCO_BnAP[TH] >
0.
This is because parity errors are not calculated
until the cycle after the data was valid on the external bus, and the EBCO_BEAR is loaded with the
address on the bus during that cycle.
If the device timings do not include at least one hold cycle, the
address may transition to the next address in a burst
or
the address of a new transaction before the
EBCO_BEAR latches the value.
10
3
1
1
Figure
16-18. Peripheral
Bus
Error
Address
Register
(EBCO_BEAR)
Address
of
Bus Error (asynchronous)
16.7.3 Peripheral Bus Error Status Register 0 (EBeO_BESRO)
The Peripheral Bus Error Status Register ° (EBCO_BESRO) records the occurrence and type of
errors for transactions attempted on behalf of the CPU, EBC
External Bus Master and PCI Bridge.
The contents of EBCO_BESRO are accessed indirectly through the EBCO_CFGADDR and
EBCO_CFGDATA registers using the
mfdcr
and
mtdcr
instructions.
It is possible to have both a parity error and a bus error during the same data transfer. If this occurs,
the bus error is detected first and EBCO_BESRO and EBCO_BEAR are updated.
In the next cycle the
parity error is detected and, if error locking is not enabled, logged
in
EBCO_BESRO.
EETO
EET1 EET2 EET3 FL3
~
+
+ + +
1
0
21
3
14
5
1
6
81911011112
14115116J7118
20121122123124
31
1
t t
t
t
t
RWSO
RWS1 RWS2 RWS3 AL3
Figure
16-19. Peripheral
Bus
Error
Status
Register
0 (EBCO_BESRO)
0:2
EETO
Error type for master 0
Master 0 is the processor instruction fetcher.
000
No
error
001 Parity error
010 Reserved
011
Reserved
100 Protection error
101
Reserved
110 External bus input error
111
External bus timeout error
3 RWSO Read/write status for master 0
o Error operation was a write operation
1 Error operation was a read operation
16-30 PPC405GP User's Manual
To Next Page
Loading...
Need help?
General
