IBM PowerPC 405GP User Manual

The dccci instruction can also be considered a "store" because it can change data by invalidating a
dirty line; however, deeei is not address-specific (it affects an entire congruence class regardless of
the operand address of the instruction).
To restrict possible damage from an instruction which can
change data and yet avoids the protection mechanism, the deeei instruction is privileged.
If data address translation is enabled, deeei can cause data storage interrupts when
TLB_entry[WR]
= 0; the operand is treated as if it were address-specific. deeei cannot cause a data
storage interrupt when ZPR[Zn]
= 00, because it is a privileged instruction.
Because deeei can cause data storage and TLB -miss interrupts, use of deeei is not recommended
when MSR[DR]
= 1; if deeei is used. Note that the specific operand address can cause an interrupt.
Architecturally,
debt and debtst are treated as "loads" because they do not change data; they cannot
cause data storage interrupts when TLB_entry[WR]
= o.
The cache block touch instructions debt and debtst are considered "speculative" loads; therefore, if a
data storage interrupt would otherwise result from the execution of
debt or debtst when
ZPR[Zn]
= 00, the instruction is treated as a no-op and the interrupt does not occur. Similarly, TLB
miss interrupts do not occur for these instructions.
Architecturally,
debf and debst are treated as "loads". Flushing or storing a line from the cache is not
architecturally considered a
"store" because a store was performed to update the cache, and debf or
debst only update main memory. Therefore, neither debf nor debst can cause data storage
interrupts when TLB_entry[WR]
= O. Because neither instruction is privileged, they can cause data
storage interrupts when ZPR[Zn]
= 00 and data address translation is enabled.
deread is a
"load" from a non-specific address, and is privileged. Therefore, it cannot cause data
storage interrupts when ZPR[Zn]
= 00 or TLB_entry[WR] = o.
iebi and iebt are considered "loads" and cannot cause data storage interrupts when
TLB_entry[WR]
= o. iebi can cause data storage interrupts when ZPR[Zn] = 00. Because iebt is
privileged, it cannot cause data storage interrupts when ZPR[Zn]
= 00.
The iecei instruction cannot change data; an instruction cache line cannot be dirty. The ieeei
instruction is privileged and is considered a load.
It does not cause data storage interrupts when
ZPR[Zn]
= 00 or TLB_entry[WR] = O.
Because ieeei can cause a TLB miss interrupt, using ieeei is not recommended when data address
translation is enabled; if it is used, note that the specific operand address can cause an interrupt.
ieread is considered a
"load" from a non-specific address, and is privileged. Therefore, it cannot
cause data storage interrupts when ZPR[Zn]
= 00 or TLB_entry[WR] = o.
6.7.3 Access Protection for String Instructions
The stswx instruction with string length equal to O(XER[TBC] = O} is a no-op.
When data address translation is enabled and the Transfer Byte Count (TBC) field of the Fixed Point
Exception Register (XER) is
0, neither Iswx nor stswx can cause TLB miss interrupts, or data storage
interrupts when ZPR[Zn]
= 0 or TLB_entry[WR] = o.
6-16
PPC405GP User's Manual Preliminary

IBM PowerPC 405GP Specifications

General

Brand	IBM
Model	PowerPC 405GP
Category	Computer Hardware
Language	English