• The hold time, EBCO_BnA.P[TH], is programmable from ° to 7 PerClk cycles. During the hold time
the
peripheral address bus remains driven with the last address and all control signals are actively
driven high. If the operation was a write, the peripheral data bus continues driving the last data
value.
•
There is no guarantee of dead cycles between transfers on the peripheral interface. If there are
back-to-back transfers to the same memory bank and the number of
hold cycles is programmed to
zero
(EBCO_BnAP[TH]=O) and EBCO_BnAP[CSN]=O, then:
- PerCSn may not
go
inactive between the back-to-back transfers.
-
If EBCO_BnAP[DEN]=O, PerDE may not become inactive between the two transfers.
-
If EBCO_BnAP[WBN]=O'and EBCO_BnAP[WBF]=O, PerWBEO:3 may not go inactive between
the back-to-back transfers.
16.2.1 Single Read Transfer
Figure 16-3 shows the peripheral interface timing for a single read transfer from a non-burst enabled
(EBCO_BnAP[BME]=O) bank. The transaction begins with the address being driven. Since this is a
single transfer, PerBLast is also driven active along with the address. If byte enable mode is enabled
for the bank (EBCO_BnAP[BEM]=1) the byte enables are also output concurrently on PerWBEO:3.
PerCSn then becomes active EBCO_BnAP[CSN]
cycles after the address, while PerDE goes low
EBCO_BnAP[DEN] cycles after PerCSn. The EBC then waits until EBCO_BnAP[TWT]+ 1 cycles have
elapsed since the start of the transaction and then reads the data bus and the peripheral error input,
PerErr.
If parity checking is enabled (EBCO_BnAP[PAR]=1) the parity is also read
at
this time. The
EBC then drives PerCSn, PerDE and PerBLast high and waits EBCO_BnAP[TH]
cycles.
Cycle
[IJj
to
to
to
trn:=
PerClk
M~V1V1Wl-,
l ! : l l ; !
I
I !
PerAddrO:31
r::;J~~Ad~d-res-s~--iC
:
~TWT+1-+j
TU
I i
'~I
~I
percsn~
PerRiW R
~
! R
PerOE~
PerBLast
Hi'
r--t:::
[
perwBEo:3
[3
•.
;
'.
.
...
' .
LJ
BEM=O
:.
, I i
PerWE
~c=J-
..
~.r-~~~--~~-
...•
~:
[
PerWBEO:3
rz::::J.,.>
.
...
,
~--=BE=--~--id
BEM=1
' ,
PerWE
-c:J~'·'~·'-~i~--~-r\iJ~···'~j
: !
iii
i
pe~~~~~~~~
. PerErr
~~~~~~
Figure 16-3. Single
Read
Transfer
16-6 PPC405GP User's Manual
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