EET4
FL4
EET5
+
+
+
10
2131
4
1516
819110
311
t t
t
RWS4
AL4
RWS5
Figure 15-16. Bus Error Status Register 1 (SDRAMO_BESR1)
0:2
EET4 Error type for master 4
Master 4 is the MAL.
000 No error
001
Reserved
01
X ECC uncorrectable error
1 XX Reserved
3
RWS4 Read/write status for master 4
o Error operation was a write operation
1 Error operation was a read operation
4 FL4
Field lock for master 4
o EET4 and RWS4 fields are unlocked
1 EET 4 and RWS4 fields are locked
5
AL4
SDRAMO_BEAR address lock for master 4
o SDRAMO_BEAR address unlocked
1 SDRAMO_BEAR address locked
6:8
EET5 Error type for master 5
Master 5 is the DMA controller.
000
No error
001
Reserved
01
X ECC uncorrectable error
1 XX Reserved
9
RWS5 Read/write status for master 5
o Error operation was a write operation
1 Error operation was a read operation
10:31
Reserved
15.5 Self-Refresh
The SDRAM controller supports self-refresh operation for applications desiring lower power. When
the
SDRAM memory is placed
in
self-refresh mode it is no longer accessible for read
or
write
accesses. Prior to
placing the SDRAM controller
in
self-refresh mode all pending and previously
queued requests targeting the SDRAM controller must be allowed to complete. Self-refresh entry is
then initiated by setting
SDRAMO_CFG[SRE]. When set, the SDRAM controller:
1.
Completes the current SDRAM operation.
2.
Issues precharge all commands to close all open pages.
3. Performs an auto-refresh
cycle.
4. Enters self-refresh mode and sets SDRAMO_STATUS[SRSTATUSl
SDRAM Controller 15-19
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