IBM PowerPC 405GP User Manual

17.10.1.6 PCI Memory To SDRAM DMA Transfer
Figure 17-65 and Figure 17-72 show a DMA transfer of data from PCI memory to SDRAM. The DMA
PLB Master executes a 4-doubleword read burst to
PCI bridge followed by a 4-doubleword write burst
to
SDRAM. For the read, PCI bridge executes a 32-byte PCI Read Line.
17.10.1.7 SDRAM To PCI Memory DMA Transfer
Figure 17-66 and Figure 17-73 show a DMA transfer of data from SDRAM to PCI memory. The DMA
PLB Master executes a 4-doubleword read burst from
SDRAM followed by a 4-doubleword write burst
to
PCI memory. PCI bridge then executes a 32-byte write on the PCI bus.
17.10.2 Asynchronous
The following diagrams are for asynchronous clocking mode. Note that all of the diagrams flow across
multiple pages. Each diagram begins with cycle 1 on the left facing page.
17-66
PPC405GP User's Manual
Preliminary

IBM PowerPC 405GP Specifications

General

Brand	IBM
Model	PowerPC 405GP
Category	Computer Hardware
Language	English