Table 18-3. DMA Transfer Priorities
DMAO_CRn[CP] Priority Level
Ob11
High
These priorities serve two purposes. First, the DMA controller arbitrates among all actively requesting
channels and selects the highest priority one for service.
If multiple channels request at the same
priority, the arbiter selects the lowest numbered channel for service. Secondly, DMAO_CRn[CP]
determines the priority of the internal PLB transactions that
the DMA controller uses to read and write
d~a.
.
18.5 Data Parity During DMA Peripheral Transfers
The DMA controller works
in
conjunction with the peripheral bus controller (EBC) to generate and
check parity during peripheral mode DMA transfers. When DMAO_CRn[PCE]=1 parity checking is
enabled for peripheral mode transfers on channel
n.
During memory-to-memory transfers any data error checking and/or correction is dependent on the
configuration of the relevant memory
controller. For example, if ECC is enabled on the SDRAM
controller, only uncorrectable errors are reported to the DMA controller. Similarly, an ESC memory
bank with parity enabled
will report an error if a parity error is encountered during a memory read
operation. See
"Peripheral Bank Access Parameters (ESCO_BnAP)" on page 16-26 for more
information on peripheral bus parity checking.
18.6 Errors
The DMA controller detects and reports three types of errors: address alignment, PLB timeout and
slave errors. The DMA controller reports errors through the channel error status bit
in
the DMA status
register (DMAO_SR[Rln]).
If the error status bit for a channel is set, the channel enable bit
(OMAO_CRn[CE]) is cleared,
disabling the channel. An interrupt signal is also presented to the
interrupt
controller ifDMAO_CRn[CIE] is set. See "DMA Interrupts" on page 18-15 for more
information on interrupt processing.
When the DMA
controller has multiple channels active, an error may be reported on the current
channel which was
in
actuality caused by a previously active channel. This causes the current
channel to have its error status bit set. Therefore, for deterministic error
analYSis with multiple DMA
channels active the PLB
slave bus controller's error status registers (the bus error address register in
particular), must be queried to isolate the actual channel which encountered the error.
In
any case,
the channel causing the errors
will eventually cause all active channels, including itself, to be
disabled.
18.6.1 Address Alignment Error
The source address (DMAO_SAn) and destination address (DMAO_DAn) registers must be aligned to
the programmed transfer width (DMAO_CRn[TW]).The address alignment
rules are outlined
in
Table 18-4.
In
addition, when a channel is configured for scatter/gather transfers, the scatter/gather
18-14
PPC405GP User's Manual
Preliminary
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