IBM PowerPC 405GP User Manual

17.3 pel Bridge Address Mapping
The following sections describe the address maps supported by the PCI bridge.
17.3.1 PLB-to-PCI Address Mapping
The PCI bridge responds as a slave on the PLB bus in several address ranges. These ranges enable
a PLB master to configure the PCI bridge, and to cause the PCI bridge to generate memory, lID,
configuration, interrupt acknowledge, and special cycles to the PCI bus. Table 17-3 shows the
address map from the
view of the PLB, that is, as decoded by the PCI bridge as a PLB slave.
Table 17-3. PLB Address Map
PLB Address
PCI Address
Range
Description
Range
OxE8000000- PCII/O
OxOOOOOOOO-
OxE800FFFF
Accesses to this range are translated to an 1/0 access on PCI OxOOOOFFFF
in the range 0 to 64KB - 1 .
OE8010000- Reserved
OE87FFFFF PCI bridge does not respond.
(Other bridges use this space for non-contiguous 1/0.)
OxE8800000- PCII/O
OxOO800000-
OxEBFFFFFF
Accesses to this range are translated to an
1/0 access on PCI Ox03FFFFFF
in the range 8MB to 64MB - 1.
OxECOOOOOO-
Reserved
OxEEBFFFFF
PCI bridge does not respond
OxEECOOOOO-
PCICO_CFGADDR and PCICO_CFGDATA
OxEECFFFFF OxEECOOOOO: PCICO_CFGADDR
OxEEC00004: PCICO_CFGDATA
OxEEC00008-0xEECFFFFF:
Reserved (can mirror
PCICO_CFGADDR and PCICO_CFGDATA).
OxEEDOOOOO- PCI Interrupt Acknowledge and Special Cycle,
OxEEDFFFFF
OxEEDOOOOO read: Interrupt Acknowledge
OxEEDOOOOO write: Special Cycle
OxEED00004-0xEEDFFFFF: Reserved (can mirror Interrupt
Acknowledge and Special Cycle).
OxEEEOOOOO- Reserved
OxEF3FFFFF
PCI bridge does not respond.
17-6
PPC405GP User's Manual
Preliminary

IBM PowerPC 405GP Specifications

General

Brand	IBM
Model	PowerPC 405GP
Category	Computer Hardware
Language	English