In address translation, the EA is combined with an 8-bit process
10
(PIO) to create a 40-bit virtual
address. The virtual address is compared to all of the TLB entries. A matching entry supplies the real
address for the storage reference. Figure
6-1
illustrates the process.
PIO
Register
i
[0:23] [24:31] I
40-bit
Virtual
Addres
Note: n is determined by page size. See
Table 6-1, ''TLB Fields Related to Page
Size," on page 6-4.
32-blt
EA
i
[0:n-1] [n:31]
Effective Page Address
[8:11+7]
[11+8:39]
Effective Page Address
32-bit Real
Address
Figure 6-1. Effective
to
Real Address Translation Flow
6.3 Translation Lookaside Buffer (TLB)
The TLB is hardware that controls translation, protection, and storage attributes. The instruction and
data units share a unified fully-associative TLB,
in
which any page entry (TLB entry) can be placed
anywhere in the TLB. TLB entries are maintained under program control. System software determines
the TLB entry replacement strategy and the format and use of page state information. A TLB entry
contains the information required to identify the page, to specify translation and protection controls,
and to specify the storage attributes.
6.3.1 Unified TLB
The unified TLB (UTLB) contains 64 entries; each has a TLBHI (tag) portion and a TLBLO (data)
portion, as described
in
Figure 6-2 on page 6-3. TLBHI contains 36 bits; TLBLO contains 32 bits.
When translation is enabled, the UTLB tag portion compares some
or
all of
EAo:21
with some or all of
the effective page number
EPN
o
:
21
, based on the size bits SIZE
o
:
2
. All
64
entries are simultaneously
checked for a match.
If an entry matches, the corresponding data portion of the UTLB provides the
6-2
PPC405GP User's Manual
Preliminary
To Next Page
Loading...
Need help?
General
