IBM PowerPC 405GP User Manual

1
0
Figure 2-3. PLB Error Address Register (PLBO_BEAR)
0:31 I Address of bus timeout error
2.1.6.3 PLB Error Status Register (PLBO_BESR)
The read/clear PLBO_BESR identifies timeout errors on PLB bus transfers, the master initiating the
transfer, and the type of transfer.
Each
PLBO_BESR[PTEn] field (n is the master ID) can be locked by the master. Once locked,
PLBO_BESR
[PTEn] fields cannot be updated if a subsequent error occurs until the corresponding
PLBO_BESR [FLCKn] field is cleared. To clear a PLBO_BESR field, write 1 to the field. Writing ° to a
PLBO_BESR field does not affect the field.
PTEO FLKO PTE1 FLK1 PTE2 FLK2 PTE3 FLK3 PTE4 FLK4 PTE5 FLK5
Figure 2-4. PLB Error Status Register (PLBO_BESR)
0 PTEO Master 0 PLB Timeout Error Status Master 0 is the processor core ICU.
o No master 0 timeout error
1 Master
0 timeout error
1
R/WO Master 0 ReadIWrite Status
o Master 0 error operation was a write
1 Master
0 ICU error operation was a read
2 FLKO Master 0 PLBO_BESR Field Lock
o Master 0 PLBO_BESR field is unlocked
1 Master 0 field is locked
3
ALKO Master 0 PLBO_BEAR Address Lock
o Master 0 PLBO_BEAR is unlocked
1 Master 0 PLBO_BEAR is locked
4
PTE1
Master 1 PLB Timeout Error Status
Master 1 is the processor core DCU.
o No master 1 timeout error
1 Master 1 timeout error
5
RIW1
Master 1 ReadIWrite Status
o Master 1 error operation was a write
1 Master 1 error operation was a read
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PPC405GP User's Manual
Preliminary

IBM PowerPC 405GP Specifications

General

Brand	IBM
Model	PowerPC 405GP
Category	Computer Hardware
Language	English