b.
If the device-paced memory is at the source memory location set PL=1.
c.
Set the source address increment, SAl, and destination address increment, DAI, as desired.
d. Set the transfer mode to device-paced memory-to-memory, TM=Ob11.
e.
Enable the channel, CE=1.
Once the DMA channel
is
configured for this mode, the external device initiates a transfer by
activating the DMAReqn input. The
PPC405GP then reads the source memory, buffers the data
in
the
DMA
controller and then outputs the data to the destination memory address. Transfers continue as
long as the controlling device maintains an active signal on DMAReqn and the channel count register
(DMAO_CTn) is non-zero.
To
pause a device paced memory-to-memory transfer, the controlling
device must deassert DMAReqn one PerClk cycle before the last cycle
in
the device-paced memory
access.
18.9.3 Software-Initiated Memory-to-Memory Transfers (Non-Deviced Paced)
To
perform a software-initiated memory-to-memory DMA transfer:
1.
Set the transfer width (DMAO_CRn[PW]) as desired.
2.
Set the source (DMAO_SAn) and destination (DMAO_DAn) address registers to the desired
memory
locations. These addresses must be aligned to the programmed transfer width
. (DMAO_CRn[PW]), otherwise an alignment error will occur.
3.
Program the count register (DMAO_CTn) for the number of transfers.
4.
Clear the channel's status bits
in
the DMA status register (DMAO_SR).
5.
In
the channel control register (DMAO_CRn):
a.
Optionally enable the DMA buffer, BEN=1.
b.
Set the source address increment, SAl, and destination address increment, DAI, as desired.
c.
Set the transfer mode to software-initiated memory-to-memory, TM=Ob10.
d. Enable the channel, CE=1.
Once the channel is enable the DMA controller transfers data from source to destination until the
channel count reaches zero. Note that memory-to-memory transfers initiated by software do not use
DMAReqn
or
DMAAckn.
Preliminary
Direct Memory Access Controller
18-21
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