To
clear TSR[ENW], use
mtspr
to write a 1 to TSR[ENW] (and to any other bits that are to
be
cleared), with 0
in
all other bit locations.
b.
Clear TSR[WIS]
in
watchdog timer handler.
It
is not expected that a watchdog interrupt will occur every time, but only if an exceptionally
high execution load delays clearing of TSR[ENW]
in
the usual time frame.
3.
Never take a watchdog interrupt.
This assumes that a recurring code
loop of reliable duration exists outside the interrupt handlers, or
that a
FIT interrupt handler is operational. This method only guarantees one watchdog timeout
period before a reset occurs.
a.
Clear TSR[WIS] in the loop or
in
FIT handler.
b.
Never use TSR[ENW] but have it set.
11.4 Timer Status Register (TSR)
The TSR can be accessed for read or write-to-clear.
Status
registers are generally set by hardware and read and cleared by software. The
mfspr
instruction reads the TSR. Clearing the TSR is performed by writing a word to the TSR, using
mtspr,
having a 1 in all fields to be cleared and a 0 in all other fields. The data written to the TSR is not direct
data, but a mask. A 1
clears the field and a 0 has no effect.
ENW
WRS
FIS
... ... ...
31
1
t t
WIS
PIS
Figure
11-6.
Timer
Status
Register
(TSR)
0
ENW Enable Next Watchdog
Software must reset TSR[ENW) = 0 after
o Action on next watchdog event is to set each watchdog timer event.
TSR[ENW)
=
1.
1 Action on next watchdog event is
governed by
TSR[WIS).
1 WIS Watchdog Interrupt Status
o No Watchdog interrupt is pending.
1 Watchdog interrupt is pending.
2:3
WRS Watchdog Reset Status
00 No Watchdog reset has occurred.
01
Core reset was forced by the watchdog.
10 Chip reset was forced by the watchdog.
11
System reset was
forc~d
by the
watchdog.
4
PIS PIT Interrupt Status
o No PIT interrupt is pending.
1
PIT interrupt is pending.
11-8
PPC405GP User's Manual Preliminary
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