โข External bus controller (EBC)
-
Flash ROM/Boot ROM interface
- Direct support for
8-,16-,
or 32-bit SRAM or external peripherals
- One external master supported
โข PCI bus, Revision 2.2 compliant (32 bit, up to 66 MHz)
-
PCI bus interface can be configured to operate synchronously
or
asynchronously
to
the PLB
-
Internal PCI bus arbiter that can be disabled for use with an external arbiter
โข DMA support for OPB and external peripherals
โข
Ethernet 10/100 Mbps (full-duplex) controller with media access layer (MAL) support
โข Interrupt controller supporting programmable interrupt handling from a variety of sources
โข
Two
8-bit serial ports (16550 compatible UARTs)
โข Inter-integrated circuit (IIC) controller
โข General
purpose I/O (GPIO) controller
1.1.2 PowerPC Processor Core Features
The PowerPC RISC fixed-point CPU features:
โข PowerPC User Instruction Set Architecture (UISA) and extensions for embedded applications
โข
Thirty-two 32-bit general purpose registers (GPRs)
โข Static branch prediction
โข Five-stage pipeline with single-cycle execution of most instructions, including loads/stores
โข Unaligned load/store
support to cache arrays, main memory, and on-Chip memory (OCM)
โข
Hardware multiply/divide for faster integer arithmetic (4-cycle multiply, 35-cycle divide)
โข Multiply-accumulate instructions
โข Enhanced string and multiple-word handling
โข
True little end ian operation
โข Programmable Interval Timer (PIT), Fixed Interval Timer (FIT), and watchdog timer
โข Forward and reverse trace from a trigger event
โข Storage control
- Separate, configurable, two-way set-associative instruction and data cache units
- Eight words (32 bytes) per cache
line
- 16KB instruction and 8KB data cache arrays
-
Instruction cache unit (ICU) non-blocking during line fills, data cache unit (DCU) non-blocking
during line fills and flushes
- Read and write line buffers
-
Instruction fetch hits are supplied from line buffer
- Data
load/store hits are supplied to line buffer
-
Programmable ICU prefetching of next sequential line into line buffer
Preliminary
Overview 1-3