16.6 EBC Registers
All EBC configuration and status registers are accessed using the PowerPC
mtdcr
and
mfdcr
instructions. Access to these registers is performed using an indirect addressing method through the
EBCO_CFGADDR and EBCO_CFGDATA registers.
Table 16-5. EBC DCR
Addresses
Register
DCR
Address
Access
Description
EBCO_CFGADDR Ox012
RIW
External Bus Controller Address
Regis~er
EBCO_CFGDATA Ox013
RIW
External Bus Controller Data Register
Table 16-6 lists the indirectly accessed EBC configuration and status registers.
Table 16-6. External
Bus
Configuration
and
Status
Registers
Mnemonic
Address
Offset
Access
Description
Page
EBCO_BOCR-EBCO_B7CR
OxOO-Ox07
RIW
Peripheral
Bank Configuration Registers 16-25
EBCO_BOAP-EBCO_B7AP
Ox10-ox17
RIW
Peripheral
Bank Access Parameters
16-26
EBCO_BEAR
Ox20
R
Peripheral Bus Error Address Register
16-29
EBCO_BESRO
Ox21
RIW
Peripheral
Bus Error Status Register 0
16-30
EBCO_BESR1
Ox22
RIW
Peripheral
Bus Error Status Register 1 16-32
EBCO_CFG
Ox23
RIW
EBC Configuration Register 16-23
To
access one of these registers, software must first write the address offset into the
EBCO_CFGADDR register. The target register can then be read or written through the
EBCO_CFGDATA DCR address. The
following PowerPC code illustrates this procedure by writing the
EBCO_BOCR
register and then reading back the written value.
li
lis
ori
mtdcr
mtdcr
mfdcr
r3,EBCO_BOCR
r4,<config
upper>
r4,r4,<config
lower>
EBCO_CFGADDR,r3
EBCO_CFGDATA,r4
r5,EBCO_CFGDATA
address
offset
upper
16-bits
of
configuration
data
lower
16-bits
of
configuratiori
data
set
offset
addr
write
config
data
read
back
config
data
16.6.1 EBC
Configuration
Register (EBCO_CFG)
The contents of EBCO_CFG are accessed indirectly through the EBCO_CFGADDR and
EBCO_CFGDATA registers using the
mfdcr
and
mtdcr
instructions.
External Bus Controller 16-23
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