IBM PowerPC 405GP User Manual

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Figure 10-13. Save/Restore Register 3 (SRR3)
SRR3 receives a copy of the MSR when a critical interrupt is taken; the MSR is restored
from
SRR3 when rfci executes.
Because critical interrupts do not automatically clear MSR[ME], SRR2 and SRR3 can be corrupted by
a machine check interrupt, if the machine check occurs
while SRR2 and SRR3 contain valid data that
has not yet been saved by the
critical interrupt handler.
10.11.4 Exception Vector Prefix Register (EVPR)
The EVPR is a 32-bit register whose high-order 16 bits contain the prefix for the address of an
interrupt
handling routine. The 16-bit interrupt vector offsets (shown in Table 10-4, "Interrupt Vector
Offsets," on page 10-27) are concatenated to the right of the high-order 16 bits of the EVPR to form
the 32-bit address of an interrupt
handling routine.
The contents of the
EVPR can be written to a GPR using the mfspr instruction. The contents of a
GPR can be written to EVPR using the mtspr instruction.
Figure
10-14 shows the EVPR bit definitions.
EVP
...
1
0 15
1
16
31
1
Figure 10-14. Exception Vector Prefix Register (EVPR)
0:15 Exception Vector Prefix
16:31 Reserved
10.11.5 Exception Syndrome Register (ESR)
The ESR is a 32-bit register whose bits help to specify the exact cause of various synchronous
interrupts. These interrupts
include instruction and data side machine checks, data storage interrupts,
and program interrupts, instruction storage interrupts, and data TLB miss interrupts.
Preliminary
Interrupt Controller Operations
10-31

IBM PowerPC 405GP Specifications

General

Brand	IBM
Model	PowerPC 405GP
Category	Computer Hardware
Language	English