- Programmable ICU prefetching of non-cacheable instructions, full line (eight words) or half line
(four words)
- Write-back or write-through DCU
write strategies
- Programmable allocation on loads and stores
- Operand forwarding during cache line fills
• Memory Management
- Translation of the 4GB logical address space into physical addresses
-
Independent enabling of instruction and data translation/protection
- Page level access control using the translation mechanism
- Software control of page replacement strategy
- Additional control over protection using zones
-
WIUOGE (write-through, cacheability, user-defined
0,
guarded, endian) storage attribute control
for each virtual memory region
• WIUOGE storage attribute control for thirty-two real 128MB regions
• PowerPC timer facilities
- 64-bit time base
-
PIT,
FIT,
and watchdog timers
- Synchronous external time base clock input
• Debug Support
- Enhanced debug support with logical operators
- Four instruction address compares (lACs)
-
Two
data address compares (DACs)
-
Two
data value compares (DVCs)
-
JTAG
instruction to write to ICU
- Forward or backward instruction tracing
• Minimized interrupt latency
• Advanced power management support
1.2 PowerPC Architecture
The PowerPC Architecture comprises three levels of standards:
• PowerPC User Instruction Set Architecture (UISA), including the base user-level instruction set,
user-level registers, programming model, data types, and addressing modes. This is referred to as
Book
I of the PowerPC Architecture.
• PowerPC Virtual Environment Architecture, describing the memory model, cache model, cache-
control instructions, address aliasing, and related issues. While accessible from the user level,
these features are intended to be accessed from within library routines provided
by
the system
software. This is referred to as Book
II
of the PowerPC Architecture.
1-4 PPC405GP User's Manual
Preliminary
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