16.3.2 Burst Write Transfer
Figure 16-6 shows the peripheral interface timing for a burst write transfer to burst enabled
(EBCO_BnAP[BME]=1) bank. The transaction begins with the address being driven. At this point the
signalling sequence depends on whether byte enable mode is enabled for the bank.
• If EBCO_BnAP[BEM]=O, byte enable mode is disabled and PerWBEO:3 are write byte enables.
In
this case, the appropriate write byte enables go low EBCO_BnAP[WBN] cycles after PerCSn. The
EBC then waits
until (EBCO_BnAP[FWT] +1) - EBCO_BnAP[WBF] cycles have elapsed since the
start of the transaction and drives PerWBEO:3 inactive. EBCO_BnAP[WBF]
cycles are then allowed
to elapse after which the address and data are output for the second element
in
the burst. As
shown
in
Figure 16-6, the EBC transfers the subsequent data items in a similar manner.
• If EBCO_BnAP[BEM]=1 , the PerWBEO:3 lines are byte enables and have the same timing as the
peripheral address bus.
In
this configuration external logic may be necessary to latch write data at
the appropriate times.
PerBLast goes
low at the beginning
of
the last transfer to indicate that the burst is ending. The EBC
then drives PerCSn and PerBLast high and waits EBCO_BnAP[TH]
cycles before allowing any
pending transfers to occur.
BEM=O
Cycle
PerClk
PerAddrO:31
PerCSn
PerR/W
PerDE
PerBLast
[
PerWBEO:3
PerWE
; i '
c::x
Address 0 X Address 1 X Address 2 X Address n C
S
~+1
~
~WT+1--+j+-
aWT+1
-¥-
~WT+l
~
i
bf;!!!!
I!!
i
it!
~
C3
G
d
BEO
BE
1
BE2
BEn
C
[
PerWBEO:3
BEM=1
' I
PerWE~
~_
...
~.'.'L-~~
__
~~~
__
~~~
__
~~~
__
~-+
__
~~
Data 0 Data 1 Data 2
Datan
C
pe~~~~~~~
E=J~~~~--j~~~~~~~~~~~~-=~~~
perErr~_.;...;...;.-..;;;..;.;;...._.;;....;......;;....;......;;....;.....
Figure 16-6. Burst Write Transfer
16-10 PPC405GP User's Manual
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