When DBCR1
[DV
nM] = 10, the comparison is an OR; at least one of the selected bytes must
compare to the appropriate bytes of DVC1.
When DBCR1 [DV nM]
= 11, the comparison is an AND-OR (halfword) comparison. This is intended
for use when DBCR1 [DVnBE] is set to
0011,0111, or 1111. Other values of DBCR1 [DVnBE] can be
compared, but the results are more easily understood using the AND and
OR comparisons.
In
Table 12-7, "not" is
-',
AND is
1\,
and OR is v.
Table 12-7.
Comparisons
Based
on
DBCR1[DVnM]
DBCR1
[DVnM]
Setting
Operation
Comparison
00
-
Undefined
01
AND
(-,DVnBEo
v (DVC1[byte 0] = data[byte 0]))
1\
(-DVnBE1
v (DVC1[byte 1] = data[byte 1]))
1\
(-,DV
nBE
2
v (DVC1 [byte 2] = data[byte 2])}
1\
(-,DVnBE
3
v (DVC1[byte
3]
= data[byte 3]))
10
OR
(DVnBEo
1\
(DVC1[byte 0] = data[byte 0])) v
(DV
nBE
1
1\
(DVC1 [byte 1] = data[byte 1])) v
(DV nBE
2
1\
(DVC1 [byte 2] = data[byte 2])) v
(DV nBE3
1\
(DVC1 [byte 3] = data[byte 3]))
11
AND-OR
(DV nBEo
1\
(DVC1 [byte 0] = data[byte 0]))
1\
(DV
nBE
1
1\
(DVC1 [byte 1] = data[byte 1])) v
(DV
nBE
2
1\
(DVC1 [byte 2] = data[byte 2]))
1\
(DV nBE3
1\
(DVC1 [byte
3]
= data[byte 1]))
12.9.15 Imprecise Debug Event
The imprecise debug event is not an independent debug event, but indicates that a debug event
occurred while MSR[DE] =
O.
This is useful in internal debug mode if a debug event occurs while in a
critical interrupt handler.
On return from interrupt, a debug interrupt occurs if MSR[DE] =
1.
If
DBSR[IDE] = 1, the debug event causing the interrupt occurred sometime earlier, not immediately
after a debug event.
Preliminary
Debugging 12-23
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